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BQ40Z50-R2 数据表(PDF) 33 Page - Texas Instruments |
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BQ40Z50-R2 数据表(HTML) 33 Page - Texas Instruments |
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33 / 51 page ![]() to Discharge FET <20 K VIL 33 bq40z50-R2 www.ti.com SLUSCS4 – JUNE 2017 Product Folder Links: bq40z50-R2 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Figure 28. System Present Pull-Down Resistor Because the System Present signal is part of the pack connector interface to the outside world, it must be protected from external electrostatic discharge events. The PRES pin has integrated ESD protection to 2 kV. External protection can be added to support higher ESD protection requirements. The TPD1E10B06 single- channel ESD protection diode (U2) can protect the input up to 30 kV, and the R8 reduces the holding current to release the internal SCR in the event that it triggers. Figure 29. System Present ESD and Short Protection 9.2.2.2.4 SMBus Communication The SMBus clock and data pins have integrated high-voltage ESD protection circuits; however, adding TPD1E10B06 ESD protection diodes (U4 and U5) and series resistors (R24 and R25) provides more robust ESD performance. |
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