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BQ40Z50-R2 数据表(PDF) 41 Page - Texas Instruments |
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BQ40Z50-R2 数据表(HTML) 41 Page - Texas Instruments |
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41 / 51 page ![]() CHARGE AND DISCHARGE PATH CURRENT FILTER SENSE RESISTOR 2 ND LEVEL PROTECTOR LEDS THERMISTORS Copyright © 2016, Texas Instruments Incorporated Pack+ C2 C3 F1 Pack± C1 BAT+ BAT± Low Level Circuits C1 J1 R1 F1 Q2 C2 Q1 C3 J1 41 bq40z50-R2 www.ti.com SLUSCS4 – JUNE 2017 Product Folder Links: bq40z50-R2 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Layout Guidelines (continued) 11.1.1 Protector FET Bypass and Pack Terminal Bypass Capacitors Use wide copper traces to lower the inductance of the bypass capacitor circuit. Figure 47 shows an example layout, demonstrating this technique. Figure 47. Use Wide Copper Traces to Lower the Inductance of Bypass Capacitors C1, C2, and C3 11.1.2 ESD Spark Gap Protect SMBus clock, data, and other communication lines from ESD with a spark gap at the connector. The pattern in Figure 48 is recommended, with 0.2-mm spacing between the points. Figure 48. Recommended Spark-Gap Pattern Helps Protect Communication Lines from ESD 11.2 Layout Example Figure 49. Top Layer |
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