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R5F104LED 数据表(PDF) 167 Page - Renesas Technology Corp

部件名 R5F104LED
功能描述  True Low Power Platform
PDF  213 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

R5F104LED 数据表(HTML) 167 Page - Renesas Technology Corp

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RL78/G14
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105
°C)
R01DS0053EJ0330 Rev. 3.30
Page 167 of 208
Aug 12, 2016
Note
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
Caution
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (for the 30- to 52-pin
products)/EVDD tolerance (for the 64- to 100-pin products)) mode for the SOp pin and SCKp pin by using port
input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics
with TTL input buffer selected.
(Remarks are listed on the page after the next page.)
(6)
Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock
output)
(TA = -40 to +105°C, 2.4 V
EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
(2/3)
Parameter
Symbol
Conditions
HS (high-speed main) mode
Unit
MIN.
MAX.
SIp setup time (to SCKp↑) Note
tSIK1
4.0 V
≤ EVDD0 ≤ 5.5 V,
2.7 V
≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 k
Ω
162
ns
2.7 V
≤ EVDD0 < 4.0 V,
2.3 V
≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 k
Ω
354
ns
2.4 V
≤ EVDD0 < 3.3 V,
1.6 V
≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 k
Ω
958
ns
SIp hold time (from SCKp↑) Note
tKSI1
4.0 V
≤ EVDD0 ≤ 5.5 V,
2.7 V
≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 k
Ω
38
ns
2.7 V
≤ EVDD0 < 4.0 V,
2.3 V
≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 k
Ω
38
ns
2.4 V
≤ EVDD0 < 3.3 V,
1.6 V
≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 k
Ω
38
ns
Delay time from SCKp↓ to SOp output Note
tKSO1
4.0 V
≤ EVDD0 ≤ 5.5 V,
2.7 V
≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 k
Ω
200
ns
2.7 V
≤ EVDD0 < 4.0 V,
2.3 V
≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 k
Ω
390
ns
2.4 V
≤ EVDD0 < 3.3 V,
1.6 V
≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 k
Ω
966
ns



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