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R5F104LED 数据表(PDF) 177 Page - Renesas Technology Corp |
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R5F104LED 数据表(HTML) 177 Page - Renesas Technology Corp |
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177 / 213 page  RL78/G14 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105 °C) R01DS0053EJ0330 Rev. 3.30 Page 177 of 208 Aug 12, 2016 3.5.2 Serial interface IICA Note 1. The first clock pulse is generated after this period when the start/restart condition is detected. Note 2. The maximum value (MAX.) of tHD: DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. Caution The values in the above table are applied even when bit 2 (PIOR02) in the peripheral I/O redirection register 0 (PIOR0) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect destination. Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Standard mode: Cb = 400 pF, Rb = 2.7 k Ω Fast mode: Cb = 320 pF, Rb = 1.1 k Ω IICA serial transfer timing Remark n = 0, 1 (TA = -40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) mode Unit Standard mode Fast mode MIN. MAX. MIN. MAX. SCLA0 clock frequency fSCL Fast mode: fCLK ≥ 3.5 MHz — — 0 400 kHz Standard mode: fCLK ≥ 1 MHz 0 100 — — kHz Setup time of restart condition tSU: STA 4.7 0.6 μs Hold time Note 1 tHD: STA 4.0 0.6 μs Hold time when SCLA0 = “L” tLOW 4.7 1.3 μs Hold time when SCLA0 = “H” tHIGH 4.0 0.6 μs Data setup time (reception) tSU: DAT 250 100 ns Data hold time (transmission) Note 2 tHD: DAT 03.45 0 0.9 μs Setup time of stop condition tSU: STO 4.0 0.6 μs Bus-free time tBUF 4.7 1.3 μs tSU: DAT tHD: STA Restart condition SCLAn SDAAn tLOW tHIGH tSU: STA tHD: STA tSU: STO Stop condition Stop condition Start condition tHD: DAT tBUF |
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