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HT82K95AE 数据表(PDF) 13 Page - Holtek Semiconductor Inc |
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HT82K95AE 数据表(HTML) 13 Page - Holtek Semiconductor Inc |
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13 / 43 page  HT82K95EE/HT82K95AE Rev. 1.50 13 April 13, 2012 extra delay of 1024 system clock pulses when the sys- tem resets (power-up, WDT time-out or RES reset) or when the system awakes from the HALT state. When a system reset occurs, an SST delay is added during the reset period. Any wake up from HALT will en- able the SST delay. The functional unit chip reset status are shown below. Program Counter 000H Interrupt Disable Prescaler Clear WDT Clear. After master reset, WDT begins counting Timer/event Counter Off Input/output Ports Input mode Stack Pointer Points to the top of the stack W a r m R e s e t W D T H A L T C o l d R e s e t R E S S y s t e m R e s e t S S T 1 0 - b i t R i p p l e C o u n t e r O S C 1 Reset Configuration The status of the registers are summarized in the following table. Register Reset (Power On) WDT Time-out (Normal Operation) RES Reset (Normal Operation) RES Reset (HALT) WDT Time-Out (HALT)* USB-Reset (Normal) USB-Reset (HALT) TMR0 xxxx xxxx 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu TMR0C 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu 00-0 1000 00-0 1000 TMR1H xxxx xxxx 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu TMR1L xxxx xxxx 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu TMR1C 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u--- 00-0 1--- 00-0 1--- Program Counter 000H 000H 000H 000H 000H 000H 000H MP0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu MP1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLH -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu STATUS --00 xxxx --1u uuuu --00 uuuu --00 uuuu --11 uuuu --uu uuuu --01 uuuu INTC -000 0000 -000 0000 --00 uuuu -000 0000 -uuu uuuu -000 0000 -000 0000 WDTS 1000 0111 1000 0111 1000 0111 1000 0111 uuuu uuuu 1000 0111 1000 0111 PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PB 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PBC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PCC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PD 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PDC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 V D D R E S Reset Circuit t S S T R E S V D D S S T T i m e - o u t C h i p R e s e t Reset Timing Chart |
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