HT82K95EE/HT82K95AE

Rev. 1.50

21

April 13, 2012

PIPE_CTRL Register is used for configuring IN (Bit=1)

or OUT (Bit=0)Pipe. The default is define IN pipe. Where

Bit0 (DATA0) of the PIPE_CTRL Register is used to set-

ting the data toggle of any endpoint (except endpoint0)

using data toggles to the value DATA0. Once the user

want the any endpoint (except endpoint0) using data

toggles to the value DATA0. the user can output a LOW

pulse to this bit. The LOW pulse period must at least 10

instruction cycle.

Endpt_EN Register is used to enable or disable the cor-

responding endpoint (except endpoint 0) Enable End-

point (Bit=1) or disable Endpoint (Bit=0)

The bitmaps are list as follows:

Register

Name

R/W

Register

Address

Bit7~Bit3 Reserved

Bit 2

Bit 1

Bit 0

Default

Value

PIPE_CTRL

R/W

01000001B

¾

Pipe 2

Pipe 1

Pipe 0

00000110

STALL

R/W

01000011B

¾

Pipe 2

Pipe 1

Pipe 0

00000110

PIPE

R

01000100B

¾

Pipe 2

Pipe 1

Pipe 0

00000000

Endpt_EN

R/W

01000001B

¾

Pipe 2

Pipe 1

Pipe 0

00000111

PIPE_CTRL (41H), STALL (43H), PIPE (44H) and Endpt_EN (47H) Registers

The SIES Register is used to indicate the present signal state which the SIE receives and also defines whether the SIE

has to change the device address automatically.

Bit No.

Function

Read/Write

Register Address

7

MNI

R/W

01000001B

6~2

¾¾

1

F0_ERR

R/W

0

Adr_set

R/W

SIES (45H) Register Table

Func. Name

R/W

Description

Adr_ set

R/W

This bit is used to configure the SIE to automatically change the device address with

the value of the Address+Remote_WakeUp Register (42H).

When this bit is set to

²1² by F/W, the SIE will update the device address with the value

of the Address+Remote_WakeUp Register (42H) after the PC Host has successfully

read the data from the device by the IN operation. The SIE will clear the bit after updat-

ing the device address. Otherwise, when this bit is cleared to

²0², the SIE will update

the device address immediately after an address is written to the Address+Re-

mote_WakeUp Register (42H)

Default 0

F0_Err

R/W

This bit is used to indicate that some errors have occurred when accessing the FIFO0.

This bit is set by SIE and cleared by F/W.

Default 0

¾¾

Unused bit, read as

²0²

NMI

R/W

This bit is used to control whether the USB interrupt is output to the MCU in NAK re-

sponse to the PC Host IN or OUT token. Only for Endpoint0

1: has only USB interrupt, data is transmitted to the PC host or data is received from

the PC Host

0: always has USB interrupt if the USB accesses FIFO0

Default 0

SIES Function Table