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7782 数据表(PDF) 47 Page - STMicroelectronics |
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7782 数据表(HTML) 47 Page - STMicroelectronics |
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47 / 63 page  47/63 M58CR032C, M58CR032D REVISION HISTORY Table 28. Document Revision History Date Version Revision Details April 2001 -01 First Issue 23-OCT-2001 -02 85ns speed class added, document classified as Preliminary Data 21-Mar-2002 -03 Document completely revised. Changes in CFI content, Program and Erase Times Table and DC Characteristics Table 06-Sep-2002 3.1 Revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, and a major revision, by incrementing the digit before the dot (revision version 03 equals 3.0). Latch Enable, L, logic level modified during Asynchronous Read/Write operations as shown in Table 3, Bus Operations. First X-Latency formula modified together with meaning of tAVK_CPU parameter in formula (under Burst Configuration Register Paragraph). Minimum VDD and VDDQ supply voltages reduced to 1.8V for 85ns class speed in Table 17, Operating and AC Measurement Conditions. ‘Number of identical-size erase block’ parameters modified in Table 32, Device Geometry Definition. |
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