13

DS734F5

5.10 Switching Characteristics—Serial Control Port–SPI Master Mode

5.10 Switching Characteristics—Serial Control Port–SPI Master Mode

Figure 5-4. Serial Control Port–SPI Master Mode Timing

Parameter

Symbol

Min

Typical

Max

Units

communication port may be limited by the firmware application.

——

2.See Section 5.7.

MHz

3.SCP_CLK PERIOD refers to the period of SCP_CLK as being used in a given application. It does not refer to a tested parameter.

—

11*DCLKP + (SCP_CLK PERIOD)/2

—

ns

SCP_CLK low time

20

—

—

ns

SCP_CLK high time

20

—

—

ns

Setup time SCP_MISO input

13

—

—

ns

Hold time SCP_MISO input

5—

—

ns

SCP_CLK low to SCP_MOSI output valid

——

8

ns

SCP_CLK low to SCP_CS# falling

7—

—

ns

SCP_CLK low to SCP_CS# rising

—

11*DCLKP + (SCP_CLK PERIOD)/2

—

ns

Bus free time between active SCP_CS#

—

3*DCLKP

—

ns

SCP_CLK falling to SCP_MOSI output high-Z

—

—

20

ns

Parameter

Symbol Min

Typical

Max

Units

——

400

kHz

SCP_CLK low time

1.25

—

—

µs

SCP_CLK high time

1.25

—

—

µs

SCP_SCK rising to SCP_SDA rising or falling for START or STOP condition

—

—

µs

START condition to SCP_CLK falling

1.25

—

—

µs

SCP_CLK falling to STOP condition

2.5

—

—

µs

Bus free time between STOP and START conditions

3—

—

µs

Setup time SCP_SDA input valid to SCP_CLK rising

100

—

—

ns

Hold time SCP_SDA input after SCP_CLK falling

20

—

—

ns

EE_CS#

SCP_CLK

SCP_MISO

SCP_MOSI

0

1267

0

56

7

A6

A5

A0

R/W

MSB

LSB

MSB

LSB