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CS48520 数据表(PDF) 4 Page - Cirrus Logic

部件名 CS48520
功能描述  Cost-effective, High-performance 32-bit DSP
PDF  23 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS48520 数据表(HTML) 4 Page - Cirrus Logic

  CS48520 Datasheet HTML 1Page - Cirrus Logic CS48520 Datasheet HTML 2Page - Cirrus Logic CS48520 Datasheet HTML 3Page - Cirrus Logic CS48520 Datasheet HTML 4Page - Cirrus Logic CS48520 Datasheet HTML 5Page - Cirrus Logic CS48520 Datasheet HTML 6Page - Cirrus Logic CS48520 Datasheet HTML 7Page - Cirrus Logic CS48520 Datasheet HTML 8Page - Cirrus Logic CS48520 Datasheet HTML 9Page - Cirrus Logic Next Button
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DS734F5
LIST OF FIGURES
Figure 5-1. RESET Timing ...................................................................................................................................... 5-11
Figure 5-2. XTI Timing............................................................................................................................................. 5-11
Figure 5-3. Serial Control Port–SPI Slave Mode Timing ......................................................................................... 5-12
Figure 5-4. Serial Control Port–SPI Master Mode Timing ....................................................................................... 5-13
Figure 5-5. Serial Control Port–I2C Slave Mode Timing.......................................................................................... 5-14
Figure 5-6. Serial Control Port–I2C Master Mode Timing........................................................................................ 5-15
Figure 5-7. Digital Audio Input (DAI) Port Timing Diagram...................................................................................... 5-15
Figure 5-8. Direct Stream Digital–Serial Audio Input Timing ................................................................................... 5-15
Figure 5-9. Digital Audio Output Port Timing, Master Mode.................................................................................... 5-17
Figure 5-10. Digital Audio Output Timing, Slave Mode (Relationship LRCLK to SCLK) ......................................... 5-17
Figure 8-1. CS48520, 48-pin LQFP Pinout.............................................................................................................. 8-19
Figure 8-2. CS48540, 48-pin LQFP Pinout.............................................................................................................. 8-20
Figure 8-3. CS48560, 48-pin LQFP......................................................................................................................... 8-21
Figure 9-1. 48-pin LQFP Package Drawing............................................................................................................. 8-22
LIST OF TABLES
Table 1-1. CS485xx Family Related Documentation................................................................................................. 1-5
Table 3-1. Device and Firmware Selection Guide ..................................................................................................... 3-6
Table 5-1. Master Mode (Output A1 Mode)............................................................................................................. 5-16
Table 5-2. Slave Mode (Output A0 Mode)............................................................................................................... 5-17
Table 6-1. Ordering Information .............................................................................................................................. 6-18
Table 7-1. Environmental, Manufacturing, and Handling Information ..................................................................... 7-18



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