14

DS734F5

5.12 Switching Characteristics—Serial Control Port–I2C Master Mode

SCP_CLK low to SCP_SDA out valid

—

—

18

ns

SCP_CLK falling to SCP_IRQ# rising

—

—

3*DCLKP + 40

ns

NAK condition to SCP_IRQ# low

—

3*DCLKP + 20

—

ns

SCP_CLK rising to SCB_BSY# low

—

3*DCLKP + 20

—

ns

communication port may be limited by the firmware application. Flow control using the SCP_BSY# pin should be implemented to prevent overflow of

the input data buffer.

Parameter

Symbol

Min

Max

Units

communication port may be limited by the firmware application.

—400

kHz

SCP_CLK low time

1.25

—

µs

SCP_CLK high time

1.25

—

µs

SCP_SCK rising to SCP_SDA rising or falling for START or STOP condition

1.25

—

µs

START condition to SCP_CLK falling

1.25

—

µs

SCP_CLK falling to STOP condition

2.5

—

µs

Bus free time between STOP and START conditions

3—

µs

Setup time SCP_SDA input valid to SCP_CLK rising

100

—

ns

Hold time SCP_SDA input after SCP_CLK falling

20

—

ns

SCP_CLK low to SCP_SDA out valid

—18

ns

Parameter

Symbol Min

Typical

Max

Units

SCP_BSY#

SCP_CLK

SCP_SDA

SCP_IRQ#

0

1

67

80

1

7

A6

A0

R/W

ACK

LSB

8

ACK

MSB

6