| 数据搜索系统,热门电子元器件搜索 |
|
WM8232 数据表(PDF) 49 Page - Cirrus Logic |
|
|
|||||||||||||||||||||||||||||
WM8232 数据表(HTML) 49 Page - Cirrus Logic |
|
49 / 141 page ![]() WM8232 Rev 4.6 49 TEST PATTERN GENERATOR WM8232 has test pattern generator which can be used for interface verification between AFE data output and back-end devices without sensor signal input. This function can be presented in several different patterns by PGPAT[1:0] and PGMARCH registers as shown below. The PGLEVEL, PGWIDTH1 and PGWIDTH2 are the parameter to define the pattern level and width. The PGLEVEL register has 16bit length, PGWIDTH1 and PGWIDTH2 has 8bit length. Note that test pattern generator is required TGSYNC input. (i.e. this can be used under TG slave mode operation only.) PGEN (register) PGPAT=00 (Fixed Pattern) 0 0 d 2d 0 0 0 d 0 d 0 d 0 nd 0 0 0 d md 0 d B A A B A B A A 0 TGSYNC (input) A PGPAT=01 (Vertical RAMP) PGPAT=10 (Horizontal RAMP) PGPAT=11 (Patch) d=PGLEVEL A=PGWIDTH1 B=PGWIDTH2 65535 0 Return to 0 at 65535 Figure 35 Test Pattern Output Data Formats A d d d d d d d d A A A A A A A B A B A B A B A B B A d d d d d d 0 0 A A A A A A A A 0 d 2d 3d 4d 5d 6d 7d A A A A A A A 0 d 2d 3d 4d 5d 6d A A A A A A A PGINV=0 B A ~d ~d ~d ~d ~d ~d A A A A A A A A A A A A A A A ~0 ~d ~2d ~3d ~4d ~5d ~6d ~7d ~0 ~d ~2d ~3d ~4d ~5d ~6d TGSYNC TGSYNC TGSYNC ~0 ~0 PGINV=1 PGPAT=01 PGPAT=10 PGPAT=11 d=PGLEVEL A=PGWIDTH1 B=PGWIDTH2 (Vertical RAMP) (Horizontal RAMP) (Patch) Figure 36 Test Pattern Output image |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |