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WM8232 数据表(PDF) 13 Page - Cirrus Logic

部件名 WM8232
功能描述  105MSPS 3-Channel AFE with Sensor
PDF  141 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

WM8232 数据表(HTML) 13 Page - Cirrus Logic

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WM8232
Rev 4.6
13
REGISTER WRITE
Figure 4 shows the sequence of operations for performing a register write. Three pins, SCK, SDI and
SEN are used for the control interface. A 16-bit address (R/W, CS0, CS1, CS2, A11 to A0) is clocked
in through SDI, MSB first, followed by an 8
–bit data word (b7 to b0), also MSB first. Setting address
bit R/W to 0 indicates that the operation is a register write. The device ID bits (CS0 and CS1) indicate
which device is being written to on a shared control bus. A register write with CS2 set to 1 writes data
to all devices on the common bus. Each bit is latched on the rising edge of SCK. When the data has
been shifted into the device, a rising edge on the SEN pin transfers the data to the appropriate internal
register.
CS2
CS1
(DSLCT2)
CS0
(DSLCT1)
DESCRIPTION
0
ID[1:0]
Indicated a device to write data
1
X
X
Writes data to all devices
Table 3 Device Identification
CS2
CS0
A2
A1
SDI
SCK
12-bit Control register address
8-bit control register data
A0
B7
B6
B5
B0
B2
B1
0
SEN
A11
CS1
CS0
3bit device ID
R/W
Figure 4 Serial Interface Register Write
REGISTER READ-BACK
Figure 5 shows register read-back in serial mode. Read-back is initiated by writing to the serial bus as
described above but with address bit R/W set to 1, followed by an 8-bit dummy data word. Writing
address (A11 to A0) will cause the contents (B7 to B0) of corresponding register in the addressed
device to be output MSB first on pin SDO (on the following edge of SCK). In this mode, the CS2
register should be set to 0.
0
CS0
A2
A1
SDI
SCK
12-bit Read back register address
8-bit outputl register data
SDO
A0
X
X
X
X
X
X
B7
B6
B5
B0
B2
B1
1
SEN
Hi-Z
Hi-Z
A11
CS1
CS0
3bit device ID
X: Don’t care
R/W
Figure 5 Serial Interface Register Read-back



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