WM8232 datasheet(21/141 Pages) CIRRUS

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WM8232

Rev 4.6

OVERALL SIGNAL FLOW SUMMARY

Figure 16 represents the processing of the video signal through the WM8232.

VRESET

VVRLC

CDS = 1

CDS = 0

VRLCEN=0

250mV*(DAC[7:0]-127.5)/127.5

analog

See parametrics for

DAC voltages.

digital

ADC BLOCK

PGA

BLOCK

OFFSET DAC

BLOCK

INPUT

SAMPLING

BLOCK

VIN is IN*

VRESET is VIN sampled during reset clamp

VRLC is voltage applied to VRLC/VBIAS pin

VIN

APGA gain

A= 0.6+0.3*AGAIN[4:0]

INPUT

INVERT

BLOCK

V1=V1 if PGAFS = 1

V1= -V1 if PGAFS = 0

Offset

DAC

RLC

DAC

VRLCEN=1

16bits

Figure 16 Overall Signal Flow

The INPUT SAMPLING BLOCK produces an effective input voltage V1. For CDS, this is the

difference between the input video level VIN and the input reset level VRESET. For non-CDS this is the

difference between the input video level VIN and the voltage on the VRLC/VBIAS pin, VVRLC, optionally

set via the RLC DAC.

The OFFSET DAC BLOCK then adds the amount of fine offset adjustment required to move the black

level of the input signal towards 0V, producing V2.

The PGA BLOCK then amplifies the white level of the input signal to maximise the ADC range,

outputting voltage V3.

The ADC BLOCK then converts the analogue signal, V3, to a 16-bit unsigned digital output, D1.

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