CS61884 datasheet(22/72 Pages) CIRRUS

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CS61884

DS485PP4

4. OPERATION

The CS61884 is a full featured line interface unit

for up to eight E1/T1/J1 lines. The device provides

an interface to twisted pair or co-axial media. A

matched impedance technique is employed that re-

duces power and eliminates the need for matching

resistors. As a result, the device can interface di-

rectly to the line through a transformer without the

need for matching resistors on the transmit side.

The receive side uses the same resistor values for

all E1/T1/J1 settings.

5. POWER-UP

On power-up, the device is held in a static state un-

til the power supply achieves approximately 70%

of the power supply voltage. Once the power sup-

ply threshold is passed, the analog circuitry is cali-

brated, the control registers are reset to their default

settings, and the various internal state machines are

reset. The reset/calibration process completes in

about 30 ms.

6. MASTER CLOCK

The CS61884 requires a 2.048 MHz or 1.544 MHz

reference clock with a minimum accuracy of ±100

ppm. This clock may be supplied from internal sys-

tem timing or a CMOS crystal oscillator and input

to the MCLK pin.

The receiver uses MCLK as a reference for clock

recovery, jitter attenuation, and the generation of

RCLK during LOS. The transmitter uses MCLK as

the transmit timing reference during a blue alarm

transmit all ones condition. In addition, MCLK

provides the reference timing for wait state genera-

tion.

In systems with a jittered transmit clock, MCLK

should not be tied to the transmit clock, a separate

crystal oscillator should drive the reference clock

input. Any jitter present on the reference clock will

not be filtered by the jitter attenuator and can cause

the CS61884 to operate incorrectly.

7. G.772 MONITORING

The receive path of channel zero of the CS61884

can be used to monitor the receive or transmit paths

of any of the other channels. The signal to be mon-

itored is multiplexed to channel zero through the

G.772 Multiplexer. The multiplexer and channel

zero then form a G.772 compliant digital Protected

Monitoring Point (PMP). When the PMP is connect-

ed to the channel, the attenuation in the signal path is

negligible across the signal band. The signal can be

observed using RPOS, RNEG, and RCLK of chan-

nelzeroor byputting channelzeroinremoteloop-

back, the signal can be observed on TTIP and

TRING of channel zero.

The G.772 monitoring function is available during

both host mode and hardware mode operation. In

host modes, individual channels are selected for

monitoring via the Performance Monitor Regis-

ter (0Bh) (See Section 14.12 on page 36)). In hard-

ware mode, individual channels are selected

through the A3:A0 pins (Refer to Table 4 below for

address settings).

NOTE: In hardware mode the A4 pin must be tied low

at all times.

Table 4. G.772 Address Selection

Address [A3:A0]

Channel Selection

0000

Monitoring Disabled

0001

Receiver Channel # 1

0010

Receiver Channel # 2

0011

Receiver Channel # 3

0100

Receiver Channel # 4

0101

Receiver Channel # 5

0110

Receiver Channel # 6

0111

Receiver Channel # 7

1000

Monitoring Disabled

1001

Transmitter Channel # 1

1010

Transmitter Channel # 2

1011

Transmitter Channel # 3

1100

Transmitter Channel # 4

1101

Transmitter Channel # 5

1110

Transmitter Channel # 6

1111

Transmitter Channel # 7

CS61884 数据表(PDF) 22 Page - Cirrus Logic

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