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Data Sheet

AD7902

Rev. B | Page 17 of 28

POWER SUPPLY

The AD7902 uses two power supply pins per ADC: a core supply

(VDDx) and a digital input/output interface supply (VIOx). VIOx

allows direct interface with any logic between 1.8 V and 5.5 V.

To reduce the number of supplies needed, VIOx and VDDx can

be tied together. The AD7902 is independent of power supply

sequencing between VIOx and VDDx. Additionally, it is very

insensitive to power supply variations over a wide frequency

range, as shown in Figure 36.

Figure 36. PSRR vs. Frequency

The AD7902 powers down automatically at the end of each

conversion phase; therefore, the power scales linearly with the

sampling rate. This makes the device ideal for low sampling

rates (of even a few hertz) and low battery-powered applications.

Figure 37. Operating Currents per ADC vs. Sampling Rate

DIGITAL INTERFACE

Although the AD7902 has a reduced number of pins, it offers

flexibility in its serial interface modes.

When in CS mode, the AD7902 is compatible with SPI, QSPI,

digital hosts, and DSPs. In this mode, the AD7902 can use either

a 3-wire or 4-wire interface. A 3-wire interface using the CNVx,

SCKx, and SDOx signals minimizes wiring connections useful,

for instance, in isolated applications. A 4-wire interface using

the SDIx, CNVx, SCKx, and SDOx signals allows CNVx, which

initiates the conversions, to be independent of the readback

timing (SDIx). This is useful in low jitter sampling or

simultaneous sampling applications.

When in chain mode, the AD7902 provides a daisy-chain feature

using the SDIx input for cascading multiple ADCs on a single

data line similar to a shift register. With the AD7902 housing

two ADCs in one package, chain mode can be utilized to

acquire data from both ADCs while using only one set of 4-wire

user interface signals.

The mode in which the device operates depends on the SDIx

level when the CNVx rising edge occurs. CS mode is selected if

SDIx is high, and chain mode is selected if SDIx is low. The

SDIx hold time is such that when SDIx and CNVx are connected

together, chain mode is always selected.

In either mode, the AD7902 offers the option of forcing a start

bit in front of the data bits. This start bit can be used as a busy

signal indicator to interrupt the digital host and trigger the data

reading. Otherwise, without a busy indicator, the user must time

out the maximum conversion time prior to readback.

The busy indicator feature is enabled as follows:

•

In CS mode when CNVx or SDIx is low when the ADC

conversion ends (see Figure 41 and Figure 45).

•

In chain mode when SCKx is high during the CNVx rising

edge (see Figure 49).

10k

100k

FREQUENCY (Hz)

0.1

0.01

0.001

100000

SAMPLING RATE (SPS)

10000

1000000

IREF

IVDD

IVIO

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