AD7902

Data Sheet

Rev. B | Page 18 of 28

CS MODE

CS Mode, 3-Wire Interface Without Busy Indicator

CS mode, using a 3-wire interface without a busy indicator, is

usually used when a single AD7902 is connected to a SPI-

compatible digital host.

The connection diagram is shown in Figure 38, and the

corresponding timing diagram is shown in Figure 39.

With SDIx tied to VIOx, a rising edge on CNVx initiates a

conversion, selects CS mode, and forces SDOx to high

impedance. When a conversion is initiated, it continues until

completion, regardless of the state of CNVx. This can be useful,

for instance, to bring CNVx low to select other SPI devices,

such as analog multiplexers.

However, to avoid generation of the busy signal indicator, CNVx

must be returned high before the minimum conversion time

elapses and then held high for the maximum possible conversion

time. When the conversion is complete, the AD7902 enters the

acquisition phase and powers down. When CNVx goes low, the

MSB is automatically output onto SDOx. The remaining data bits

are clocked by subsequent SCKx falling edges. The data is valid on

both SCKx edges. Although the rising edge can be used to capture

the data, a digital host using the falling edge of SCKx allows a

faster reading rate, provided that it has an acceptable hold time.

(whichever occurs first), SDOx returns to high impedance.

Figure 38. CS Mode, 3-Wire Interface Without a Busy Indicator Connection Diagram (SDIx High)

Figure 39. CS Mode, 3-Wire Interface Without a Busy Indicator Serial Interface Timing (SDI High)

AD7902

SDIx

SDOx

CNVx

SCKx

CONVERT

DATA IN

CLK

DIGITAL HOST

VIOx

SDIx = 1

CNVx

ACQUISITION

ACQUISITION

CONVERSION

SCKx

1

2

3

14

15

16

SDOx

D15

D14

D13

D1

D0