AD7902

Data Sheet

Rev. B | Page 20 of 28

CS Mode, 4-Wire Interface Without Busy Indicator

CS mode, using a 4-wire interface without a busy indicator, is

usually used when both ADCs within the AD7902 are

connected to a SPI-compatible digital host.

See Figure 42 for an AD7902 connection diagram example. The

corresponding timing diagram is shown in Figure 43.

With SDIx high, a rising edge on CNVx initiates a conversion,

selects CS mode, and forces SDOx to high impedance. In this

mode, CNVx must be held high during the conversion phase

and the subsequent data readback. (If SDIx and CNVx are low,

SDOx is driven low.) Prior to the minimum conversion time,

SDIx can be used to select other SPI devices, such as analog

multiplexers, but SDIx must be returned high before the

minimum conversion time elapses and then held high for the

maximum possible conversion time to avoid the generation of

the busy signal indicator. When the conversion is complete, the

AD7902 enters the acquisition phase and powers down. Each

ADC result can be read by bringing its respective SDIx input

low, which consequently outputs the MSB onto SDOx. The

remaining data bits are then clocked by subsequent SCKx falling

edges. The data is valid on both SCKx edges. Although the rising

edge can be used to capture the data, a digital host using the

SCKx falling edge allows a faster reading rate, provided it has an

SDIx goes high (whichever occurs first), SDOx returns to high

impedance, and another ADC result can be read.

Figure 42. CS Mode, 4-Wire Interface Without a Busy Indicator Connection Diagram

Figure 43. CS Mode, 4-Wire Interface Without a Busy Indicator Serial Interface Timing

AD7902

ADC2

SDI2

SDO2

CNV2

SCK2

CONVERT

DATA IN

CLK

DIGITAL HOST

CS1

CS2

AD7902

ADC1

SDI1

SDO1

CNV1

SCK1

ACQUISITION

ACQUISITION

CONVERSION

SCKx

CNVx

SDOx

1

2

3

14

15

16

17

18

30

31

32

SDI1 (CS1)

SDI2 (CS2)