AD7989-1/AD7989-5

Data Sheet

Rev. B | Page 16 of 24

SINGLE-ENDED TO DIFFERENTIAL DRIVER

For applications using a single-ended analog signal, either

bipolar or unipolar, the ADA4941-1 single-ended to differential

driver allows a differential input to the device. The schematic is

shown in Figure 29.

R1 and R2 set the attenuation ratio between the input range and

depending on the desired input resistance, signal bandwidth,

antialiasing, and noise contribution. For example, for the ±10 V

range with a 4 kΩ impedance, R2 = 1 kΩ and R1 = 4 kΩ.

R3 and R4 set the common mode on the IN− input, and R5 and R6

set the common mode on the IN+ input of the ADC. Ensure the

range with a single supply, R3 = 8.45 kΩ, R4 = 11.8 kΩ, R5 =

10.5 kΩ, and R6 = 9.76 kΩ.

Figure 29. Single-Ended to Differential Driver Circuit

VOLTAGE REFERENCE INPUT

The AD7989-1/AD7989-5 voltage reference input, REF, has a

dynamic input impedance and must, therefore, be driven by a

low impedance source with efficient decoupling between the

REF and GND pins, as explained in the Layout section.

When REF is driven by a very low impedance source (for example,

a reference buffer using the AD8031 or the ADA4807-1), a 10 μF

(X5R, 0805 size) ceramic chip capacitor is appropriate for optimum

performance.

If using an unbuffered reference voltage, the decoupling value

depends on the reference used. For instance, a 22 μF (X5R,

1206 size) ceramic chip capacitor is appropriate for optimum

performance using a low temperature drift ADR435 reference.

If desired, use a reference decoupling capacitor with values as

small as 2.2 μF with a minimal impact on performance,

especially DNL.

Regardless, there is no need for an additional lower value ceramic

decoupling capacitor (for example, 100 nF) between the REF

and GND pins.

POWER SUPPLY

The AD7989-1/AD7989-5 use two power supply pins: a core

supply (VDD) and a digital input/output interface supply (VIO).

VIO allows direct interface with any logic between 1.8 V and 5.5 V.

To reduce the number of supplies needed, tie VIO and VDD

together. The AD7989-1/AD7989-5 are independent of power

supply sequencing between VIO and VDD. Additionally, they are

insensitive to power supply variations over a wide frequency

range, as shown in Figure 30.

Figure 30. PSRR vs. Frequency

The AD7989-1/AD7989-5 power down automatically at the end

of each conversion phase.

DIGITAL INTERFACE

Although the AD7989-1/AD7989-5 have a reduced number of

pins, they offer flexibility in their serial interface modes.

When in CS mode, the AD7989-1/AD7989-5 are compatible

with SPI, queued serial peripheral interface (QSPI), digital hosts,

and digital signal processors (DSPs). In this mode, the AD7989-1/

AD7989-5 can use either a 3-wire or 4-wire interface. A 3-wire

interface using the CNV, SCK, and SDO signals minimizes

wiring connections, which is useful, for instance, in isolated

applications. A 4-wire interface using the SDI/CS, CNV, SCK,

and SDO signals allows CNV, which initiates the conversions, to be

independent of the readback timing (SDI). This is useful in low

jitter sampling or simultaneous sampling applications.

When in chain mode, the AD7989-1/AD7989-5 provide a daisy-

chain feature using the SDI input for cascading multiple ADCs

on a single data line, similar to a shift register.

The mode in which the device operates depends on the SDI/CS

level when the CNV rising edge occurs. CS mode is selected if

SDI/CS is high, and chain mode is selected if SDI/CS is low. The

SDI/CS hold time is such that when SDI/CS and CNV are

connected together, chain mode is always selected. The user

must timeout the maximum conversion time prior to readback.

20Ω

20Ω

10µF

R1

100nF

+2.5V

+5V REF

+5.2V

–0.2V

R2

R4

R6

±10V,

±5V, ..

R3

R5

REF

VDD

GND

IN+

IN–

AD7989-1/

AD7989-5

2.7nF

2.7nF

ADA4941

IN

FB

OUTP

OUTN

REF

100nF

95

90

85

80

75

70

65

60

1

10

100

1k

FREQUENCY (kHz)