Data Sheet

AD7989-1/AD7989-5

Rev. B | Page 19 of 24

CHAIN MODE

This mode can daisy-chain multiple AD7989-1/AD7989-5

devices on a 3-wire serial interface. This feature reduces

component count and wiring connections, for example, in

isolated multiconverter applications or for systems with a

limited interfacing capacity. Data readback is analogous to

clocking a shift register.

A connection diagram example using two AD7989-1/AD7989-5

devices is shown in Figure 35, and the corresponding timing is

given in Figure 36.

When SDI/CS and CNV are low, SDO is driven low. With SCK

low, a rising edge on CNV initiates a conversion, and selects the

chain mode.

In this mode, CNV is held high during the conversion phase

and the subsequent data readback. When the conversion is

complete, the MSB is output onto SDO and the AD7989-1/

AD7989-5 enter the acquisition phase and power down. The

remaining data bits stored in the internal shift register are

clocked by subsequent SCK falling edges. For each ADC, SDI

feeds the input of the internal shift register and is clocked by the

SCK falling edge. Each ADC in the chain outputs its data MSB

first, and 18 × N clocks are required to read back the N ADCs.

The data is valid on both SCK edges. Although the rising edge

can capture the data, a digital host using the SCK falling edge

allows a faster reading rate and, consequently, more AD7989-1/

AD7989-5 devices in the chain, provided that the digital host has

an acceptable hold time. The maximum conversion rate may be

reduced due to the total readback time.

Figure 35. Chain Mode Connection Diagram

Figure 36. Chain Mode Serial Interface Timing

CONVERT

DATA IN

CLK

DIGITAL HOST

AD7989-1/

AD7989-5

SDO

CNV

B

SCK

AD7989-1/

AD7989-5

SDO

CNV

A

SCK

SDI/CS

SDI/CS

SCK

123

34

35

36

CONVERSION

ACQUISITION

ACQUISITION

CNV

16

17

19

20

18