AD7989-5BCPZ-R2 datasheet(18/24 Pages) AD

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AD7989-1/AD7989-5

Data Sheet

Rev. B | Page 18 of 24

CS MODE, 4-WIRE

This mode is usually used when multiple AD7989-1/AD7989-5

devices are connected to an SPI-compatible digital host.

A connection diagram example using two AD7989-1/AD7989-5

devices is shown in Figure 33, and the corresponding timing is

given in Figure 34.

With SDI high, a rising edge on CNV initiates a conversion,

selects SDI/CS mode, and forces SDO to high impedance. In

this mode, CNV must be held high during the conversion phase

and the subsequent data readback. If SDI/CS and CNV are low,

SDO is driven low.

Prior to the minimum conversion time, SDI/CS can select other

SPI devices, such as analog multiplexers, but SDI/CS must be

returned high before the minimum conversion time elapses and

then held high for the maximum possible conversion time.

When the conversion is complete, the AD7989-1/AD7989-5

enter the acquisition phase and power down. Each ADC result

can be read by bringing its SDI/CS input low, which consequently

outputs the MSB onto SDO. The remaining data bits are then

clocked by subsequent SCK falling edges. The data is valid on

both SCK edges. Although the rising edge can capture the data,

a digital host using the SCK falling edge allows a faster reading

rate, provided it has an acceptable hold time. After the 18th SCK

falling edge or when SDI/CS goes high (whichever occurs first),

SDO returns to high impedance and another AD7989-1/AD7989-5

can be read.

Figure 33. CS Mode, 4-Wire Connection Diagram

Figure 34. CS Mode, 4-Wire Serial Interface Timing

AD7989-1/

AD7989-5

SDO

CNV

SCK

CONVERT

DATA IN

CLK

DIGITAL HOST

CS1

CS2

AD7989-1/

AD7989-5

SDO

CNV

SCK

SDI/CS

SDO

D17

D16

D15

tDIS

SCK

tHSDO

tDSDO

tEN

CONVERSION

ACQUISITION

tCONV

tCYC

tACQ

ACQUISITION

CNV

tSSDICNV

tHSDICNV

tSCK

tSCKL

tSCKH

D17

D16

SDI/CS (CS1)

SDI/CS (CS2)

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