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PIC12CE673 数据表(PDF) 55 Page - Microchip Technology |
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PIC12CE673 数据表(HTML) 55 Page - Microchip Technology |
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55 / 116 page  © 1998 Microchip Technology Inc. Preliminary DS40181B-page 55 PIC12CE67X FIGURE 9-15: INT PIN INTERRUPT TIMING Q2 Q1 Q3 Q4 Q2 Q1 Q3 Q4 Q2 Q1 Q3 Q4 Q2 Q1 Q3 Q4 Q2 Q1 Q3 Q4 OSC1 CLKOUT INT pin INTF flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction fetched Instruction executed Interrupt Latency PC PC+1 PC+1 0004h 0005h Inst (0004h) Inst (0005h) Dummy Cycle Inst (PC) Inst (PC+1) Inst (PC-1) Inst (0004h) Dummy Cycle Inst (PC) — 1 4 5 1 Note 1: INTF flag is sampled here (every Q1). 2: Interrupt latency = 3-4 Tcy where Tcy = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT is available only in INTRC and EXTRC oscillator modes. 4: For minimum width of INT pulse, refer to AC specs. 5: INTF is enabled to be set anytime during the Q4-Q1 cycles. 2 3 |
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