AD9246-125EB datasheet(25/45 Pages) AD

25 / 45 page

AD9246

Rev. A | Page 24 of 44

MEMORY MAP

READING THE MEMORY MAP REGISTER TABLE

Each row in the memory map register table has eight address

locations. The memory map is roughly divided into three

sections: the chip configuration registers map (Address 0x00 to

Address 0x02), the device index and transfer registers map

(Address 0xFF), and the ADC functions map (Address 0x08 to

Address 0x18).

Table 15 displays the register address number in hexadecimal in

the first column. The last column displays the default value for

each hexadecimal address. The Bit 7 (MSB) column is the start

of the default hexadecimal value given. For example, Hexadecimal

Address 0x14, output_phase, has a hexadecimal default value of

0x00. This means Bit 3 = 0, Bit 2 = 0, Bit 1 = 1, and Bit 0 = 1 or

0011 in binary. This setting is the default output clock or DCO

phase adjust option. The default value adjusts the DCO phase

90° relative to the nominal DCO edge and 180° relative to the

data edge. For more information on this function, consult the

Interfacing to High Speed ADCs via SPI User Manual.

Open Locations

Locations marked as open are currently not supported for this

device. When required, these locations should be written with

0s. Writing to these locations is required only when part of an

address location is open (for example, Address 0x14). If the

entire address location is open (Address 0x13), then the address

location does not need to be written.

Default Values

Coming out of reset, critical registers are loaded with default

values. The default values for the registers are shown in Table 15.

Logic Levels

An explanation of two registers follows:

•

“Bit is set” is synonymous with “Bit is set to Logic 1” or

“Writing Logic 1 for the bit.”

•

“Clear a bit” is synonymous with “Bit is set to Logic 0” or

“Writing Logic 0 for the bit.”

SPI-Accessible Features

A list of features accessible via the SPI and a brief description of

what the user can do with these features follow. These features

are described in detail in the Interfacing to High Speed ADCs via

SPI User Manual.

•

Modes:

Set either power-down or standby mode.

•

Clock:

Access the DCS via the SPI.

•

Offset:

Digitally adjust the converter offset.

•

Test I/O:

Set test modes to have known data on output bits.

•

Output Mode:

Set up outputs; vary the strength of the

output drivers.

•

Output Phase:

Set the output clock polarity.

•

VREF:

Set the reference voltage.

DON’T CARE

SDIO

SCLK

CSB

tDH

tHI

tCLK

tLO

tDS

R/W

A12

A11

A10

Figure 57. Serial Port Interface Timing Diagram

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