TGA4548-SM

17 – 20 GHz 10 W GaN Power Amplifier

Data Sheet Rev. C, April 24, 2017 | Subject to change without notice

8 of 12

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Pad Configuration and Description

Top View

Bottom View

Pad No.

Label

Description

1, 3, 7, 13, 15, 21

GND

Ground. May be grounded on PCB.

2

RFIN

RF input, matched to 50

, AC coupled.

4, 24

VG1

Gate voltage. Bias network is required; can be biased from either pin, and non-biased pin can be

left open; see Application Circuit on page 4 as an example.

5, 23

VG2

Gate voltage. Bias network is required; can be biased from either pin, and non-biased pin can be

left open; see Application Circuit on page 4 as an example.

6, 22

VG3

Gate voltage. Bias network is required; can be biased from either pin, and non-biased pin can be

left open; see Application Circuit on page 4 as an example.

8, 20

VD1

Drain voltage. Bias network is required; see Application circuit on page 4 as an example.

9, 19

VD2

Drain voltage. Bias network is required; see Application circuit on page 4 as an example.

10, 18

VD3

Drain voltage. Bias network is required; see Application circuit on page 4 as an example.

11, 17

VDET

Detector diode output voltage. Varies with RF output power.

12, 16

VREF

Reference diode output voltage

14

RFOUT

RF output, matched to 50

, AC coupled.

25

GND

Backside paddle. Multiple vias should be employed to minimize inductance and thermal resistance;

see Mounting Configuration on page 11 for suggested footprint.