AD6640

–12–

REV. A

ENCODE

ENCODE

AD6640

R

T1–1T

SINE

SOURCE

Figure 11. Sine Source–Differential ENCODE

If a low jitter ECL clock is available, another option is to ac-couple

a differential ECL signal to the ENCODE input pins as shown in

Figure 12. The capacitors shown here should be chip capacitors

but do not need to be of the low inductance variety.

ENCODE

ENCODE

AD6640

ECL

GATE

0.1 F

0.1 F

510

510

Figure 12. Differential ECL for ENCODE

As a final alternative, the ECL gate may be replaced by an ECL

comparator. The input to the comparator could then be a logic

signal or a sine signal.

ENCODE

ENCODE

AD6640

0.1 F

0.1 F

50

AD96687 (1/2)

510

510

Figure 13. ECL Comparator for ENCODE

Driving the Analog Input

Because the AD6640 operates from a single 5 V supply, the

analog input voltage range is offset from ground by 2.4 V. Each

analog input connects through a 450

Ω resistor to the 2.4 V bias

voltage and to the input of a differential buffer (Figure 14). This

resistor network on the input properly biases the followers for

maximum linearity and range. Therefore, the analog source driving

the AD6640 should be ac-coupled to the input pins. Since the

differential input impedance of the AD6640 is 0.9 k

Ω, the analog

input power requirement is only –3 dBm, simplifying the drive

amplifier in many cases.

AD6640

450

2.4V

REFERENCE

AIN

0.01 F

450

BUF

BUF

BUF

AIN

0.1 F

Figure 14. Differential Analog Inputs

To take full advantage of this high input impedance, a 20:1 trans-

former would be required. This is a large ratio and could result

in unsatisfactory performance. In this case, a lower step-up

Ω,

along with a 4:1 transformer, the input would match to a 50

Ω

source with a full-scale drive of 4 dBm (Figure 15). Note that the

input resistance of 900

Ω. The external resistor value can be

calculated from the following equation:

=

1

1

Z

–

1

900

where Z is the desired impedance (200

Ω for a 4:1 transformer

with 50

Ω input source).

AIN

0.01 F

AIN

0.1 F

1:4

ANALOG

INPUT

SIGNAL

AD6640

Figure 15. Transformer-Coupled Analog Input Signal

If the lower drive power is attractive, a combination transformer

match and LC match could be employed that would use a 4:1

transformer with an LC as shown in Figure 16. This solution is

useful when good performance in the third Nyquist zone is

required. Such a requirement arises when digitizing high inter-

mediate frequencies in communications receivers.

AIN

0.01 F

AIN

0.1 F

1:4

AD6640

–j125

+j100

ANALOG

SIGNAL

AT

–3dBm

Figure 16. Low Power Drive Circuit

In applications where gain is needed but dc-coupling is not

necessary, an extension of Figure 16 is recommended. A 50

Ω

gain block may be placed in front of the LC matching network.

Such gain blocks are readily available for commercial applications.

These low cost modules can have excellent NF and intermodulation

performance. This circuit is especially good for the “IF” receiver

application previously mentioned.

In applications where dc-coupling is required, the circuit in

Figure 17 can be used. It should be noted that the addition of

circuitry for dc-coupling may compromise performance in terms of

noise, offset, and dynamic performance. This circuit requires an

inverting and noninverting signal path. Additionally, an offset must

be generated so that the analog input to each pin is centered

near 2.4 V. Since the input is differential, small differences in

the dc voltage at each input can translate into an offset for the

circuit. The same holds true for gain mismatch. Therefore, some

means of adjusting the gain and offset between the sides should