AD6640

–20–

REV. A

The signal-to-noise ratio (SNR) for an ADC can be predicted.

When normalized to ADC codes, the following equation accurately

predicts the SNR based on jitter, average DNL error, and thermal

noise. Each of these terms contributes to the noise within the

converter.

SNR

Ft rms

V

ANALOG

NOISE rms

=

+

+

+

()













































–

log

/

20

2

1

22

2

12

2

12

2

12

π

ε

J

where:

=rms jitter of the ENCODE (rms sum of ENCODE

source and internal ENCODE circuitry)

ε

= average DNL of the ADC (typically 0.51 LSB)

the ADC (typically 0.707 LSB)

Processing Gain

Processing gain is the improvement in signal-to-noise ratio (SNR)

gained through oversampling and digital filtering. Most of this

processing gain is accomplished using the channelizer chips.

These special purpose DSP chips not only provide channel selec-

tion and filtering but also a data rate reduction. The required rate

reduction is accomplished through a process called decimation.

The term decimation rate is used to indicate the ratio of input

data rate to output data rate. For example, if the input data

rate is 65 MSPS and the output data rate is 1.25 MSPS,

then the decimation rate is 52.

Large processing gains may be achieved in the decimation and

filtering process. The purpose of the channelizer, beyond tuning,

is to provide the narrow-band filtering and selectivity that tradi-

tionally have been provided by the ceramic or crystal filters of a

narrow-band receiver. This narrow-band filtering is the source of

the processing gain associated with a wide band receiver and

is simply the ratio of the pass-band to whole band expressed in

dB. For example, if a 30 kHz AMPS signal is being digitized

with an AD6640 sampling at 65 MSPS, the ratio would be

0.015 MHz/32.5 MHz. Expressed in log form, the processing

gain is –10

× log (0.015 MHz/32.5 MHz) or 33.4 dB.

Additional filtering and noise reduction techniques can be achieved

through DSP techniques; many applications do use additional

process gains through proprietary noise reduction algorithms.

Overcoming Static Nonlinearities with Dither

Typically, high resolution data converters use multistage tech-

niques to achieve high bit resolution without large comparator

arrays that would be required if traditional “flash” ADC techniques

were employed. The multistage converter typically provides

better wafer yields meaning lower cost and much lower power.

However, since the AD6640 is a multistage device, certain por-

tions of the circuit are used repetitively as the analog input sweeps

from one end of the converter range to the other. Although the

worst DNL error may be less than an LSB, the repetitive nature

of the transfer function can play havoc with low level dynamic

signals. Spurious signals for a full-scale input may be –80 dBc. At

36 dB below full scale, however, these repetitive DNL errors may

cause spurious-free dynamic range (SFDR) to fall below 80 dBFS

as shown in TPC 14.

A common technique for randomizing and reducing the effects

of repetitive static linearity is through the use of dither. The

purpose of dither is to force the repetitive nature of static linear-

ity to appear as if it were random. Then, the average linearity

over the range of dither will dominate SFDR performance. In

the AD6640, the repetitive cycle is every 15.625 mV p-p.

To ensure adequate randomization, 5.3 mV rms is required;

this equates to a total dither power of –32.5 dBm. This will

randomize the DNL errors over the complete range of the

residue converter. Although lower levels of dither such as that

from previous analog stages will reduce some of the linearity

errors, the full effect will only be gained with this larger dither.

Increasing dither even more may be used to reduce some of the

global INL errors. However, signals much larger than the mVs

proposed here begin to reduce the usable dynamic range of the

converter.

Even with the 5.3 mV rms of noise suggested, SNR would be

limited to 36 dB if injected as broadband noise. To avoid this

problem, noise may be injected as an out-of-band signal. Typically,

other frequency not used by the receiver. The bandwidth of the

noise is several hundred kilohertz. By band-limiting and control-

ling its location in frequency, large levels of dither may be intro-

duced into the receiver without seriously disrupting receiver

performance. The result can be a marked improvement in the

SFDR of the data converter.

TPC 17 shows the same converter shown earlier but with this

injection of dither (see TPC 14).

AD600

A

A

REF

2.2k

1 F

0.1 F

39

390

16k

+15V

NC202

NOISE

DIODE

(NoiseCom)

+5V

–5V

1k

2k

OP27

OPTIONAL HIGH

POWER DRIVE

CIRCUIT

LOW CONTROL

(0V–1V)

Figure 30. Noise Source (Dither Generator)

The simplest method for generating dither is through the use of

a noise diode (Figure 30). In this circuit, the noise diode NC202

generates the reference noise that is gained up and driven by the

AD600 and OP27 amplifier chain. The level of noise may be

controlled by either presetting the control voltage when the

system is set up, or by using a digital-to-analog converter (DAC)

to adjust the noise level based on input signal conditions. Once

generated, the signal must be introduced to the receiver strip.

The easiest method is to inject the signal into the drive chain

after the last down conversion as shown in Figure 31.