AD6640

–13–

REV. A

Layout Information

The schematic of the evaluation board (Figure 18) represents

a typical implementation of the AD6640. The pinout of the

AD6640 facilitates ease of use and the implementation of high

frequency/high resolution design practices. All of the digital

outputs are on one side while the other sides contain all of the

inputs. It is highly recommended that high quality ceramic chip

capacitors be used to decouple each supply pin to ground directly

at the device. Depending on the configuration used for the

ENCODE and analog inputs, one or more capacitors are required

on those input pins. The capacitors used on the

ENCODE and

previously in this data sheet.

A multilayer board is recommended to achieve best results. Care

should be taken when placing the digital output runs. Because the

digital outputs have such a high slew rate, the capacitive loading

on the digital outputs should be minimized. Circuit traces for

the digital outputs should be kept short and connect directly to

the receiving gate (broken only by the insertion of the series

resistor). Digital data lines should be kept clear of analog and

ENCODE traces.

Evaluation Boards

The evaluation board for the AD6640 is very straightforward,

consisting of power, signal inputs, and digital outputs. The

evaluation board includes the option for an onboard clock oscil-

lator for the ENCODE.

Power to the analog supply pins is connected via banana jacks.

pins of the AD6640.

digital supply connection also powers the digital gates on the PCB.

By maintaining separate analog and digital power supplies, degra-

dation in SNR and SFDR is kept to a minimum. Total power

requirement is approximately 200 mA. This configuration allows

for easy evaluation of different logic families (i.e., connection

to a 3.3 V logic board).

The analog input is connected via J2 and is transformer-coupled

to the AD6640 (see Driving the Analog Input section). The

onboard termination resistor is 270

Ω. This resistor, in parallel

with the AD6640’s input resistance (900

Ω), provides a 50 Ω load

to the analog source driving the 1:4 transformer. If a different

input impedance is required, replace R16 by using the equation

R16

=

1

1

Z

−

1

900

where Z is desired input impedance (200

Ω for a 4:1 transformer

with 50

Ω source).

The analog input range of the PCB is

±0.5 V (i.e., signal ac-coupled

to AD6640).

The ENCODE signal may be generated using an onboard crystal

oscillator, U1. The oscillator is socketed and may be replaced by

an external ENCODE source via J1. If an external source is used,

it should be a high quality TTL source. A transformer converts

the single-ended TTL signal to a differential clock (see Encoding

the AD6640 section). Since the ENCODE is coupled with a

transformer, a sine wave could have been used; note, however,

that U5 requires TTL levels to function properly.

be implemented. The addition of small value resistors between the

AD9631 and the AD6640 will prevent oscillation due to the

capacitive input of the ADC.

62

SIGNAL

SOURCE

AD9631

15

467

0.1 F

OP279

(1/2)

OP279

(1/2)

750

1000

78

350

AD6640

AIN

425

467

0.1 F

0.01 F

127

350

AD9631

15

AIN

350

Figure 17. DC-Coupled Analog Input Circuit

Power Supplies

Care should be taken when selecting a power source. Linear

supplies are strongly recommended as switching supplies tend to

have radiated components that may be “received” by the

AD6640. Each of the power supply pins should be decoupled as

closely to the package as possible using 0.1

µF chip capacitors.

The AD6640 has separate digital and analog 5 V pins. The analog

best performance is achieved when the supplies are separate. This

is because the fast digital output swings can couple switching

to the same supply as the digital circuitry). The AD6640 is specified

Output Loading

Care must be taken when designing the data receivers for the

AD6640. It is recommended that the digital outputs drive a series

resistor (e.g., 348

Ω) followed by a gate like the 74LCX574.

To minimize capacitive loading, there should only be one gate on

each output pin. An example of this is shown in the evaluation

board schematic shown in Figure 18. The digital outputs of the

AD6640 have a constant rise time output stage. The output

gate combined with PCB trace and through hole will have a load

of approximately 10 pF. Therefore, as each bit switches:

1V

1ns









of dynamic current per bit will flow in or

out of the device. A full-scale transition can cause up to 120 mA

(12 bits

10 mA/bit) of current to flow through the digital output

stages. The series resistor will minimize the output currents that

can flow in the output stage. These switching currents are con-

should be avoided since they can appreciably add to the dynamic

switching currents of the AD6640.