VS6552V02CSLASHT2 datasheet(7/26 Pages) STMICROELECTRONICS

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VS6552

3.2.3 Image Statistics

VS6552 generates image statistics which can be

used by STV0974 as an input to an auto exposure

controller (AEC), automatic gain controller (AGC)

and automatic white balance (AWB). .

3.3 Device Operating Modes

3.3.1 Standby

This is the lowest power consumption mode. I2C

communications to STV0974 are not supported in

this mode. The clock input pad, PLL and the video

blocks are powered down.

3.3.2 Sleep Mode

Sleep mode preserves the contents of the I2C reg-

ister map. I2C communications to STV0974 are

supported in this mode. The sleep mode is select-

ed via a serial interface command sent by

STV0974. The data pads go high at the end of the

current frame. At this point the video block and

PLL power down. The internal video timing is reset

to the start of a video frame in preparation for the

enabling of active video. The values of the serial

interface registers like exposure and gain are pre-

served. The system clock must remain active to al-

low communication with the sensor.

3.3.3 Clock Active Mode

This mode is similar to ‘sleep mode’ except that

the PLL is now powered up to permit a PCLKP/

PCLKN signal to be delivered to STV0974. The

PDATAP/PDATAN pads remain inactive. The vid-

eo block is powered down.

3.3.4 Idle Mode

VCAP is generated. The analog video block is now

powered up but the array is held in reset and the

output PDATAP/PDATAN pads remain high.

3.3.5 Video

The VS6552 streams live video to the STV0974.

Table 4. VS6552 Power-up Sequence

3.4 Power Management

VS6552 requires a dual power supply. The analog

circuits are powered by a nominal 2.8 V supply

while the digital logic and digital I/O are powered

by a nominal 1.8 V supply.

3.4.1 Power-up, Power-down Procedures

The power up and power down procedures are de-

tailed in the following Figure 3.

Mode

Design block powered down

Video data

inhibit

I2C

Digital

PLL & CLK

pinsa b

a.PLL (Phase Locked Loop) generates fast system clock for STV0974

b.PLL, PCLKP and PCLKN pins

Output pins

Analog

Standby

(PDN low)

Yes

Sleep

Yes

Clock

active

Yes

Idle

Yes

Video

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