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VS6552V02C/T2 数据表(PDF) 12 Page - STMicroelectronics |
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VS6552V02C/T2 数据表(HTML) 12 Page - STMicroelectronics |
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12 / 26 page ![]() VS6552 12/26 Table 13. vLVDS Interface AC Electrical Characteristics Table 14. vLVDS TIming Characteristics Figure 5. VisionLink AC timing Symbol Parameter description Min. Typ. Max. Unit Vod Differential voltage swinga,b a.Supplies of VDIG = 1.8 V and VANA = 2.8 V, Temperature = 25 °C b.Measured over a 100 Ohm load 100 150 200 mV Vcm Common mode voltage (self biasing) 0.8 0.9 1.0 V RO Output Impedance 40 140 W IDR Drive current range (internally set by bias circuit) 0.5 1.5 2 mA Symbol Parameter Min. Typ. Max. Unit fPCLKP/ PCLKN PCLKP/PCLKN clock frequency - - 120 MHz tPCLKP/ PCLKN PCLKP/PCLKN clock period 8.3 - 100 ns PCLKP/PCLKN duty cycle 26 - 74 % tLOW Low period of PCLKP/PCLKN 1.66 - ns tHIGH High period of PCLKP/PCLKN 1.66 - ns tRISE Rise time of PDATAP/PDATAN, PCLKP/ PCLKN 0.3 - 0.5 ns tFALL Fall time of PDATAP/PDATAN, PCLKP/ PCLKN 0.3 - 0.5 ns tHD;DAT Data hold time 3 - - ns tSU;DAT Data set-up time 1 - - ns PDATAP/ PDATAN PCLKP/ PCLKN VDIG/2 VDIG / 2 tHD;DAT tSU;DAT tFALL tHIGH tRISE tLOW tPCLKP/PCLKN |
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