Revision 1.1

Jun. 7, 1999

-19-

GL640USB, GL640USB-A

0:

the ping-pong FIFO is used for end1

DMATXEN

-

enable DMA/EPP engine to access data into TXFIFO

DMARXEN

-

enable DMA/EPP engine to move data from RXFIFO into external

Device

TXNULL

-

Set this bit to transmit a zero-byte data on endp1

This bit will be cleared by hardware automatically.

TX64ONLY

-

Transmit 64-byte packet only

When this bit is set, data left in FIFO will not be sent if it is not

64 bytes.

Note: When LINKFF is set and LINKDIR is gonna to change, LINKFF should be cleared to ‘0’first and

then change LINKDIR and set LINKFF again.

FFCTL ( offset 99h )

W/O

W/O

W/O

R/W

R/W

R/W

R/W

R/W

FF0RST

RXFFRST

TXFFRST

STSTXEN

DRXDIS/

DTX1EN

DTX0EN

CTLRXDIS

CTLTXEN

CTLTXEN -

enable endpoint 0 transmitting

This bit is cleared by hardware when CTLTX interrupt is set.

CTLRXDIS

-

disable endpoint 0 receiving

DTXEN

-

turn on this bit to enable endpoint 1 data packet transmission.

If LINKFF=1, it indicates the TXFIFO0 is ready.

This bit is cleared by hardware when DATATX interrupt is set.

DRXDIS

-

disable RXFIFO receiving

If this bit is set, NAK will be responded to the OUT token.

Data in RXFIFO is kept unchanged.

If LINKFF=1, this bit means the TXFIFO1 is ready.

STSTXEN -

enable endpoint 3 transmitting

This bit is cleared by hardware when STSTX interrupt is set.

TXFFRST

-

reset TXFIFO, cleared by hardware itself.

RXFFRST -

reset RXFIFO, cleared by hardware itself

FF0RST

-

reset CTL/STS FIFO, cleared by hardware itself

FF0DAT ( offset 9Ah )