Revision 1.1

Jun. 7, 1999

-18-

GL640USB, GL640USB-A

STSTX

Reserved

Reserved

Default=8’h00

STSTX

-

The interrupt endpoint 3 transmits a status packet completely

CTLDAT/STSDAT ( offset 96h )

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

CTLDAT7

CTLDAT6

CTLDAT5

CTLDAT4

CTLDAT3

CTLDAT2

CTLDAT1

CTLDAT0

Read:

Pop data from endp0/endp3 FIFO.

Write:

Push data into endp0/endp3 FIFO.

CTLLEN/STSLEN ( offset 97h )

R/O

R/O

R/W

R/W

R/W

R/W

R/W

RXSETUP

RXOUT

DATOG

CTLLEN3

CTLLEN2

CTLLEN1

CTLLEN0

For the received OUT/SETUP transaction on endp0/endp3, read this register to check the data size and data

toggle, and then read the received data from CTLDAT/STSDAT register. To transmit data on endp0/endp3, first

push data into endp0/endp3 FIFO, and then write this register to set data size and data toggle. Finally, turn on

CTLTXEN or STSTXEN bit to enable the data transmission.

CTLLEN3-0

-

Length of the received/transmitted endp0/endp3 data

DATOG

-

Data toggle of the received/transmitted endp0/endp3 data

RXOUT

-

The received transaction is an OUT transaction

RXSETUP -

The received transaction is a SETUP transaction

FFCFG ( offset 98h )

R/W

R/W

R/W

R/W

R/W

R/W

TX64ONLY

TXNULL

DMARXEN/

EPPRXEN

DMATXEN/E

PPTXEN

LINKDIR

LINKFF

Default=8’h00

This register is used to control TX/RX FIFO and DMA/EPP engine operation.

LINKFF

-

link RXFIFO to TXFIFO together to form ping-pong FIFO

LINKDIR

-

This bit is valid only when LINKFF is set to 1.

1:

the ping-pong FIFO is used for end2