Revision 1.1

Jun. 7, 1999

-23-

GL640USB, GL640USB-A

When this bit is set to ‘1’, D+ and D- pin will be driven to low so that no connect

will be detected on the host side.

EVTFLG ( offset 11h )

W/O

R/W1C

R/W1C

R/W1C

R/W1C

R/W1C

S_CTLRX

WAKEUP

RESUME

SUSPD

EP0TX

EP0RX

This register is the main USB interrupt flag for endpoint 0 and power management. The firmware

detects endpoint 0 transaction via EP0RX and EP0TX. If firmware can’t handle the received endpoint 0

control data, then firmware should write ‘1’to S_CTLRX and EP0RX. By this, the interrupt will redirect to

the external DMA interrupt and the CTLRX bit of USBFLG register will be set. For power management,

when a USB suspend is detected, the SUSPD bit will be set to ‘1’. If the USB host put the bus to ‘K’ state

during suspend, then the RESUME bit will be set to ‘1’. If a remote-wake-up event is detected, then the

WAKEUP bit will be set to ‘1’.

All those interrupt status bits can be written ‘1’ to clear.

EP0RX

-

Endpoint 0 receives a data packet.

EP0TX

-

Endpoint 0 transmits a data packet completely.

SUSPD

-

USB suspend detected

RESUME

-

USB resume detected

WAKEUP- remote-wake-up event is detected during suspend state

The event is

DMA mode:

WAKEVT bit is set

EPP mode: INT_ pin is asserted low

S_CTLRX- Write 1 to set CTLRX bit of USBFLG

All the data in endp0/endp3 FIFO are left unchanged.

DEVADR ( offset 12h )

R/W

R/W

R/W

R/W

R/W

R/W

R/W

DEVADR6

DEVADR5

DEVADR4

DEVADR3

DEVADR2

DEVADR1

DEVADR0

This register is used to set USB device address.

Default=8’h00