M41ST87WMX6 datasheet(12/42 Pages) STMICROELECTRONICS

12 / 42 page

M41ST87Y, M41ST87W

12/42

READ Mode

In this mode the master reads the M41ST87Y/W

slave after setting the slave address (see Figure

9., page 12). Following the WRITE Mode Control

Bit (R/W=0) and the Acknowledge Bit, the word

address 'An' is written to the on-chip address

pointer. Next the START condition and slave ad-

dress are repeated followed by the READ Mode

Control Bit (R/W=1). At this point the master trans-

mitter becomes the master receiver.

The data byte which was addressed will be trans-

mitted and the master receiver will send an Ac-

knowledge Bit to the slave transmitter. The

address pointer is only incremented on reception

of an Acknowledge Clock. The M41ST87Y/W

slave transmitter will now place the data byte at

address An+1 on the bus, the master receiver

reads and acknowledges the new byte and the ad-

dress pointer is incremented to An+2.

This cycle of reading consecutive addresses will

continue until the master receiver sends a STOP

condition to the slave transmitter (see Figure

10., page 13).

The system-to-user transfer of clock data will be

halted whenever the address being read is a clock

address (00h to 07h). The update will resume ei-

ther due to a Stop Condition or when the pointer

increments to a non-clock or RAM address.

Note: This is true both in READ Mode and WRITE

Mode.

An alternate READ Mode may also be implement-

ed whereby the master reads the M41ST87Y/W

slave without first writing to the (volatile) address

pointer. The first address that is read is the last

one

stored

the

pointer

(see

Figure

11., page 13).

Figure 9. Slave Address Location

AI00602

R/W

SLAVE ADDRESS

START

100

M41ST87WMX6 数据表(PDF) 12 Page - STMicroelectronics

M41ST87WMX6 数据表(HTML) 12 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

数据表下载