M41ST87WMX6 datasheet(16/42 Pages) STMICROELECTRONICS

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M41ST87Y, M41ST87W

16/42

Tamper Connect Mode Bit (TCM1 and TCM2).

This bit indicates whether the position of the exter-

nal switch selected by the user is in the Normally

Open

(TCMX = '1')

Normally

Closed

(TCMX = '0') position (see Figure 14., page 16 and

Figure 16., page 17).

Tamper Polarity Mode Bits (TPM1 and TPM2).

The state of this bit indicates whether the Tamper

Pin Input will be taken high (to VOUT if TPMX = '1')

or low (to VSS if TPMX = '0') during a tamper event

(see

Figure

14., page 16

and

Figure

16., page 17).

Figure 14. Tamper Detect Connection Options

Note: These options are connected to those in Table 3.

Note: 1. If the CLRXEXT Bit is set, a second Tamper to VOUT (TPM2 = '1') during tCLR will not be detected.

2. If the CLRXEXT Bit is set, a second Tamper to VOUT (TPM2 = '1') will trigger automatically.

3. Optional external resistor to VCC allows the user to bypass sampling when power is “on.”

Table 3. Tamper Detection Truth Table

Note: 1. No battery current drawn during battery back-up.

Option

Mode

TCMX

TPMX

Normally Open/Tamper to GND(1)

Normally Open/Tamper to VOUT

(1)

III

Normally Closed/Tamper to GND

Normally Closed/Tamper to VOUT

AI07075

TPIN

TAMPER HI

(TPMX = 1)

TAMPER LO

(TPMX = 0)

VOUT

(1)

TPIN

NORMALLY

CLOSED

(TCMX = 0)

NORMALLY

OPEN

(TCMX = 1)

IV.

II.

III.

TPIN

VOUT

(2)

TCHI/TCLO = 0

Ω

10M

Ω

TCHI/TCLO = 1

TCHI/TCLO = 0

TCHI/TCLO = 1

Ω

10M

Ω

VOUT (Int)

VCC

(3)

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