M41ST87WMX6 datasheet(6/42 Pages) STMICROELECTRONICS

6 / 42 page

M41ST87Y, M41ST87W

6/42

Figure 2. Logic Diagram

Note: 1. Open drain output

2. Programmable output (Open drain or Full-CMOS)

Figure 3. 28-pin, 300mil SOIC (MX)

Connections

Note: No Function (NF) and No Connect (NC) pins should be tied

to VSS. Pins 1, 2, 3, and 4 are internally shorted together.

Table 1. Signal Names

Note: 1. Open drain output

2. Programmable output (Open drain or Full-CMOS)

3. Should be connected to VSS.

AI07023

SCL

VCC

M41ST87Y

M41ST87W

VSS

VBAT

SDA

RSTIN1

IRQ/OUT

(1)

SQW/FT

(2)

WDI

RSTIN2

TP1IN

PFI2

TP2IN

PFI1

ECON

RST

(1)

PFO1

(2)

PFO2

(2)

VOUT

F32k

(1)

TPCLR

AI07025b

RSTIN1

RSTIN2

PFI2

SQW/FT

WDI

IRQ/OUT

F32k

VOUT

TP1IN

PFI1

SCL

TPCLR

PFO1

ECON

VSS

VBAT

TP2IN

SDA

RST

VCC

M41ST87Y

M41ST87W

PFO2

ECON

Conditioned Chip Enable Output

External Chip Enable

IRQ/OUT(1)

Interrupt/Out Output

(Open drain)

PFI1

Power Fail Input 1

PFI2

Power Fail Input 2

PFO1

(2)

Power Fail Output 1

PFO2

(2)

Power Fail Output 2

RST(1)

Reset Output (Open Drain)

RSTIN1

Reset 1 Input

RSTIN2

Reset 2 Input

SCL

Serial Clock Input

SDA

Serial Data Input/Output

SQW/FT(2)

Square Wave Output/Frequency

Test

WDI

Watchdog Input

VCC

Supply Voltage

VOUT

Voltage Output

VSS

Ground

F32k

(1)

32kHz Square Wave Output

(Open drain)

TP1IN

Tamper Pin 1 Input

TP2IN

Tamper Pin 2 Input

TPCLR

Tamper Pin RAM Clear

VBAT

Positive Battery Pin Input

NF(3)

No Function

NC(3)

No Connect

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M41ST87WMX6 数据表(PDF) 6 Page - STMicroelectronics

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