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DSP56321 数据表 (PDF) - Freescale Semiconductor, Inc

DSP56321 Datasheet PDF - Freescale Semiconductor, Inc
部件名 DSP56321
下载  DSP56321 下载

文件大小   1563.93 Kbytes
  84 Pages
制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc
功能描述 24-Bit Digital Signal Processor

DSP56321 Datasheet (PDF)

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DSP56321 Datasheet PDF - Freescale Semiconductor, Inc

部件名 DSP56321
下载  DSP56321 Click to download

文件大小   1563.93 Kbytes
  84 Pages
制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc
功能描述 24-Bit Digital Signal Processor

DSP56321 数据表 (HTML) - Freescale Semiconductor, Inc

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DSP56321 产品详情

The Freescale DSP56321, a member of the DSP56300 DSP family, supports networking, security encryption, and home entertainment using a high-performance, single-clock-cycle-per- instruction engine (DSP56000 code compatible), a barrel shifter, 24-bit addressing, an instruction cache, and a direct memory access (DMA) controller (see Figure 1).

The DSP56321 offers 275 million multiply- accumulates per second (MMACS) performance, attaining 550 MMACS when the EFCOP is in use. It operates with an internal 275 MHz clock with a 1.6 volt core and independent 3.3 volt input/output (I/O) power. By operating in parallel with the core, the EFCOP provides overall enhanced performance and signal quality with no impact on channel throughput or total channel support. This device is pin-compatible with the Freescale DSP56303, DSP56L307, DSP56309, and DSP56311.



Features

High-Performance DSP56300 Core

• 275 million multiply-accumulates per second (MMACS) (550 MMACS using the EFCOP in filtering applications) with a 275 MHz clock at 1.6 V core and 3.3 V I/O

• Object code compatible with the DSP56000 core with highly parallel instruction set

• Data arithmetic logic unit (Data ALU) with fully pipelined 24 × 24-bit parallel Multiplier-Accumulator (MAC), 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing), conditional ALU instructions, and 24-bit or 16-bit arithmetic support under software control

• Program control unit (PCU) with position independent code (PIC) support, addressing modes optimized for DSP applications (including immediate offsets), internal instruction cache controller, internal memory expandable hardware stack, nested hardware DO loops, and fast auto-return interrupts

• Direct memory access (DMA) with six DMA channels supporting internal and external accesses; one-, two-, and three-dimensional transfers (including circular buffering); end-of-block-transfer interrupts; and triggering from interrupt lines and all peripherals

• Phase-lock loop (PLL) allows change of low-power divide factor (DF) without loss of lock and output clock with skew elimination

• Hardware debugging support including on-chip emulation (OnCE) module, Joint Test Action Group (JTAG) test access port (TAP)



Enhanced Filter Coprocessor (EFCOP)

• Internal 24 × 24-bit filtering and echo-cancellation coprocessor that runs in parallel to the DSP core

• Operation at the same frequency as the core (up to 275 MHz)

• Support for a variety of filter modes, some of which are optimized for cellular base station applications:

   • Real finite impulse response (FIR) with real taps

   • Complex FIR with complex taps

   • Complex FIR generating pure real or pure imaginary outputs alternately

   • A 4-bit decimation factor in FIR filters, thus providing a decimation ratio up to 16

   • Direct form 1 (DFI) Infinite Impulse Response (IIR) filter

   • Direct form 2 (DFII) IIR filter

   • Four scaling factors (1, 4, 8, 16) for IIR output

   • Adaptive FIR filter with true least mean square (LMS) coefficient updates

   • Adaptive FIR filter with delayed LMS coefficient updates



Internal Peripherals

• Enhanced 8-bit parallel host interface (HI08) supports a variety of buses (for example, ISA) and provides glueless connection to a number of industry-standard microcomputers, microprocessors, and DSPs

• Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters (allows six-channel home theater)

• Serial communications interface (SCI) with baud rate generator

• Triple timer module

• Up to 34 programmable general-purpose input/output (GPIO) pins, depending on which peripherals are enabled



 




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关于 Freescale Semiconductor, Inc


Freescale Semiconductor是一家美国半导体公司,成立于1948年。
该公司是微控制器,传感器和其他半导体产品的领先提供商,用于汽车,工业和消费市场中的各种应用。
Freescale的产品以其高性能,低功耗和较小的外形而闻名。
该公司是NXP半导体在2015年收购的,其产品和技术继续以NXP品牌开发和出售。

*此信息仅供一般参考,对于因上述信息造成的任何损失或损害,我们概不负责。




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