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DSP56321 数据表(PDF) 8 Page - Freescale Semiconductor, Inc |
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DSP56321 数据表(HTML) 8 Page - Freescale Semiconductor, Inc |
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8 / 84 page  DSP56321 Technical Data, Rev. 11 1-2 Freescale Semiconductor Signals/Connections Figure 1-1. Signals Identified by Functional Group Notes: 1. The HI08 port supports a non-multiplexed or a multiplexed bus, single or double data strobe (DS), and single or double host request (HR) configurations. Since each of these modes is configured independently, any combination of these modes is possible. These HI08 signals can also be configured alternatively as GPIO signals (PB[0–15]). Signals with dual designations (for example, HAS/HAS) have configurable polarity. 2. The ESSI0, ESSI1, and SCI signals are multiplexed with the Port C GPIO signals (PC[0–5]), Port D GPIO signals (PD[0–5]), and Port E GPIO signals (PE[0–2]), respectively. 3. TIO[0–2] can be configured as GPIO signals. DSP56321 24 18 External Address Bus External Data Bus External Bus Control Enhanced Synchronous Serial Interface Port 0 (ESSI0)2 Timers3 OnCE/ JTAG Port Power Inputs: Core Logic I/O Address Bus Data Bus Bus Control HI08 ESSI/SCI/Timer A[0–17] D[0–23] AA[0–3] RD WR TA BR BG BB TCK TDI TDO TMS TRST DE VCCQL VCCQH VCCA VCCD VCCC VCCH VCCS 5 Serial Communications Interface (SCI) Port2 4 2 2 Grounds: Ground plane GND 66 Interrupt/ Mode Control MODA MODB MODC MODD RESET PINIT Host Interface (HI08) Port1 Non-Multiplexed Bus H[0–7] HA0 HA1 HA2 HCS/HCS Single DS HRW HDS/HDS Single HR HREQ/HREQ HACK/HACK RXD TXD SCLK SC0[0–2] SCK0 SRD0 STD0 TIO0 TIO1 TIO2 8 3 3 EXTAL XTAL Clock Enhanced Synchronous Serial Interface Port 1 (ESSI1) 2 SC1[0–2] SCK1 SRD1 STD1 3 Multiplexed Bus HAD[0–7] HAS/HAS HA8 HA9 HA10 Double DS HRD/HRD HWR/HWR Double HR HTRQ/HTRQ HRRQ/HRRQ Port B GPIO PB[0–7] PB8 PB9 PB10 PB13 PB11 PB12 PB14 PB15 Port E GPIO PE0 PE1 PE2 Port C GPIO PC[0–2] PC3 PC4 PC5 Port D GPIO PD[0–2] PD3 PD4 PD5 Timer GPIO TIO0 TIO1 TIO2 Port A 4 IRQA IRQB IRQC IRQD 3 RESET During Reset After Reset NMI |
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