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DSP56321 数据表(PDF) 75 Page - Freescale Semiconductor, Inc |
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DSP56321 数据表(HTML) 75 Page - Freescale Semiconductor, Inc |
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75 / 84 page  DSP56321 Technical Data, Rev. 11 Freescale Semiconductor A-11 ; Register Addresses Of DMA0 M_DSR0 EQU $FFFFEF ; DMA0 Source Address Register M_DDR0 EQU $FFFFEE ; DMA0 Destination Address Register M_DCO0 EQU $FFFFED ; DMA0 Counter M_DCR0 EQU $FFFFEC ; DMA0 Control Register ; Register Addresses Of DMA1 M_DSR1 EQU $FFFFEB ; DMA1 Source Address Register M_DDR1 EQU $FFFFEA ; DMA1 Destination Address Register M_DCO1 EQU $FFFFE9 ; DMA1 Counter M_DCR1 EQU $FFFFE8 ; DMA1 Control Register ; Register Addresses Of DMA2 M_DSR2 EQU $FFFFE7 ; DMA2 Source Address Register M_DDR2 EQU $FFFFE6 ; DMA2 Destination Address Register M_DCO2 EQU $FFFFE5 ; DMA2 Counter M_DCR2 EQU $FFFFE4 ; DMA2 Control Register ; Register Addresses Of DMA4 M_DSR3 EQU $FFFFE3 ; DMA3 Source Address Register M_DDR3 EQU $FFFFE2 ; DMA3 Destination Address Register M_DCO3 EQU $FFFFE1 ; DMA3 Counter M_DCR3 EQU $FFFFE0 ; DMA3 Control Register ; Register Addresses Of DMA4 M_DSR4 EQU $FFFFDF ; DMA4 Source Address Register M_DDR4 EQU $FFFFDE ; DMA4 Destination Address Register M_DCO4 EQU $FFFFDD ; DMA4 Counter M_DCR4 EQU $FFFFDC ; DMA4 Control Register ; Register Addresses Of DMA5 M_DSR5 EQU $FFFFDB ; DMA5 Source Address Register M_DDR5 EQU $FFFFDA ; DMA5 Destination Address Register M_DCO5 EQU $FFFFD9 ; DMA5 Counter M_DCR5 EQU $FFFFD8 ; DMA5 Control Register ; DMA Control Register M_DSS EQU $3 ; DMA Source Space Mask (DSS0-Dss1) M_DSS0 EQU 0 ; DMA Source Memory space 0 M_DSS1 EQU 1 ; DMA Source Memory space 1 M_DDS EQU $C ; DMA Destination Space Mask (DDS-DDS1) M_DDS0 EQU 2 ; DMA Destination Memory Space 0 M_DDS1 EQU 3 ; DMA Destination Memory Space 1 M_DAM EQU $3f0 ; DMA Address Mode Mask (DAM5-DAM0) M_DAM0 EQU 4 ; DMA Address Mode 0 M_DAM1 EQU 5 ; DMA Address Mode 1 M_DAM2 EQU 6 ; DMA Address Mode 2 M_DAM3 EQU 7 ; DMA Address Mode 3 M_DAM4 EQU 8 ; DMA Address Mode 4 M_DAM5 EQU 9 ; DMA Address Mode 5 M_D3D EQU 10 ; DMA Three Dimensional Mode M_DRS EQU $F800 ; DMA Request Source Mask (DRS0-DRS4) M_DCON EQU 16 ; DMA Continuous Mode M_DPR EQU $60000 ; DMA Channel Priority |
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