DSP56321 datasheet(7/84 Pages) FREESCALE

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DSP56321 Technical Data, Rev. 11

Freescale Semiconductor

1-1

Signals/Connections

The DSP56321 input and output signals are organized into functional groups as shown in Table 1-1. Figure 1-1

diagrams the DSP56321 signals by functional group. The remainder of this chapter describes the signal pins in

each functional group.

Note:

This chapter refers to a number of configuration registers used to select individual multiplexed signal

functionality. See the DSP56321 Reference Manual for details on these configuration registers.

Table 1-1.

DSP56321 Functional Signal Groupings

Functional Group

Number of

Signals

Power (VCC)

Ground (GND)

Clock

Address bus

Port A1

Data bus

Bus control

Interrupt and mode control

Host interface (HI08)

Port B

Enhanced synchronous serial interface (ESSI)

Ports C and D3

Serial communication interface (SCI)

Port E

Timer

OnCE/JTAG Port

Notes:

Port A signals define the external memory interface port, including the external address bus, data bus, and control signals.

Port B signals are the HI08 port signals multiplexed with the GPIO signals.

Port C and D signals are the two ESSI port signals multiplexed with the GPIO signals.

Port E signals are the SCI port signals multiplexed with the GPIO signals.

Eight signal lines are not connected internally. These are designated as no connect (NC) in the package description (see

Chapter 3). There are also two reserved lines.

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