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DSP56321 数据表(PDF) 72 Page - Freescale Semiconductor, Inc |
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DSP56321 数据表(HTML) 72 Page - Freescale Semiconductor, Inc |
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72 / 84 page ![]() DSP56321 Technical Data, Rev. 11 A-8 Freescale Semiconductor Power Consumption Benchmark M_FSL1 EQU 8 ; Frame Sync Length 1 M_FSR EQU 9 ; Frame Sync Relative Timing M_FSP EQU 10 ; Frame Sync Polarity M_CKP EQU 11 ; Clock Polarity M_SYN EQU 12 ; Sync/Async Control M_MOD EQU 13 ; SSI Mode Select M_SSTE EQU $1C000 ; SSI Transmit enable Mask M_SSTE2 EQU 14 ; SSI Transmit #2 Enable M_SSTE1 EQU 15 ; SSI Transmit #1 Enable M_SSTE0 EQU 16 ; SSI Transmit #0 Enable M_SSRE EQU 17 ; SSI Receive Enable M_SSTIE EQU 18 ; SSI Transmit Interrupt Enable M_SSRIE EQU 19 ; SSI Receive Interrupt Enable M_STLIE EQU 20 ; SSI Transmit Last Slot Interrupt Enable M_SRLIE EQU 21 ; SSI Receive Last Slot Interrupt Enable M_STEIE EQU 22 ; SSI Transmit Error Interrupt Enable M_SREIE EQU 23 ; SI Receive Error Interrupt Enable ; SSI Status Register Bit Flags M_IF EQU $3 ; Serial Input Flag Mask M_IF0 EQU 0 ; Serial Input Flag 0 M_IF1 EQU 1 ; Serial Input Flag 1 M_TFS EQU 2 ; Transmit Frame Sync Flag M_RFS EQU 3 ; Receive Frame Sync Flag M_TUE EQU 4 ; Transmitter Underrun Error FLag M_ROE EQU 5 ; Receiver Overrun Error Flag M_TDE EQU 6 ; Transmit Data Register Empty M_RDF EQU 7 ; Receive Data Register Full ; SSI Transmit Slot Mask Register A M_SSTSA EQU $FFFF ; SSI Transmit Slot Bits Mask A (TS0-TS15) ; SSI Transmit Slot Mask Register B M_SSTSB EQU $FFFF ; SSI Transmit Slot Bits Mask B (TS16-TS31) ; SSI Receive Slot Mask Register A M_SSRSA EQU $FFFF ; SSI Receive Slot Bits Mask A (RS0-RS15) ; SSI Receive Slot Mask Register B M_SSRSB EQU $FFFF ; SSI Receive Slot Bits Mask B (RS16-RS31) ;------------------------------------------------------------------------ ; ; EQUATES for Exception Processing ; ;------------------------------------------------------------------------ ; Register Addresses M_IPRC EQU $FFFFFF ; Interrupt Priority Register Core M_IPRP EQU $FFFFFE ; Interrupt Priority Register Peripheral ; Interrupt Priority Register Core (IPRC) M_IAL EQU $7 ; IRQA Mode Mask |
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