ATSAMB11XR datasheet(31/87 Pages) MICROCHIP

31 / 87 page

Figure 7-4. Bank 5 Block 3

The bits that are not depicted in the above register description are all reserved for future use.

7.3.1

26 MHz XO Calibration information

Information for both ATSAMB11-XR2100A and ATSAMB11-ZR210CA will be pre-programmed.

7.3.2

BT Address

These bits contain the BT address used by the user application. For ATSAMB11-ZR210CA modules, the

BT address is pre-programmed. For ATSAMB11-XR2100A, the user must purchase the MAC address

from IEEE and program it to the designated bit locations of the non-volatile memory.

7.3.3

Flash Memory

The ATSAMB11-XR2100A and ATSAMB11-ZR210CA have 256 kB of Flash memory, stacked on top of

the MCU and BLE SoC. It is accessed through the SPI Flash controller.

Flash memory features are:

•

256 bytes per programmable page

•

Uniform 4 kB Sectors, 32 kB & 64 kB Blocks

•

Sector Erase (4 Kbyte)

•

Block Erase (32K or 64 Kbyte)

•

Page program up to 256 bytes <1 ms

•

More than 100,000 erase/write cycles and more than 20-year data retention

•

2.3V to 3.6V supply range

Refer to BluSDK SMART BLE API Software Development Guide for the memory map of this memory

section.

ATSAMB11XR/ZR

Datasheet Preliminary

DS70005342A-page 31

ATSAMB11XR 数据表(PDF) 31 Page - Microchip Technology