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ATSAMB11XR 数据表(PDF) 70 Page - Microchip Technology |
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ATSAMB11XR 数据表(HTML) 70 Page - Microchip Technology |
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70 / 87 page  Figure 13-3. 20-pin IDC JTAG Connector Table 13-2. 20-pin IDC JTAG Connector Header Signal Name Description SWDCLK Serial wire clock pin SWDIO Serial wire bidirectional data pin nRESET Target device reset pin, active-low Vcc Target voltage GND Ground GND* These pins are reserved for firmware extension purposes. They can be left open or connected to GND in normal debug environment. They are not essential for SWD in general. 13.3 Unused or Unconnected Pins Internal pull-down for unused pins must be enabled to acheive the lowest current leakage. ATSAMB11XR/ZR © 2017 Microchip Technology Inc. Datasheet Preliminary DS70005342A-page 70 |
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