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L9678P 数据表(PDF) 102 Page - STMicroelectronics |
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L9678P 数据表(HTML) 102 Page - STMicroelectronics |
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102 / 203 page  SPI interface L9678P, L9678P-S 102/203 DocID029274 Rev 3 5.1.42 Safing records response mask registers (SAF_RESP_MASK_x) Safing record response mask for record 1 (SAF_RESP_MASK_1) Safing record response mask for record 2 (SAF_RESP_MASK_2) Safing record response mask for record 3 (SAF_RESP_MASK_3) Safing record response mask for record 4 (SAF_RESP_MASK_4) Address: A6 (SAF_RESP_MASK_1) A7 (SAF_RESP_MASK_2) A8 (SAF_RESP_MASK_3) A9 (SAF_RESP_MASK_4) Type: RW Buffer: $A600 (SAF_RESP_MASK_1) $A700 (SAF_RESP_MASK_2) $A800 (SAF_RESP_MASK_3) $A900 (SAF_RESP_MASK_4) Reset: $804C (SAF_RESP_MASK_1) $804E (SAF_RESP_MASK_2) $8050 (SAF_RESP_MASK_3) $8052 (SAF_RESP_MASK_4) 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOSI - SAF_RESP_MASKx[15:0] MISO 0 0 0 0 SAF_RESP_MASKx[15:0] SAF_RESP_MASKx [15:0] 0000 0000 0000 Safing Response Mask for safing record x - 16-bit response mask that is bit- wise ANDed with MISO data from SPI monitor Updated by SSM_RESET or SPI write while in DIAG state |
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