9

PC755/745

2138D–HIREL–06/03

Notes:

1. OV

the PLL (after filtering to become AVDD). These columns serve as a reference for the nominal voltage supported on a given

or supply voltages see Table 3.

to OGND (selects 1.8V/2.0V).

4. Uses one of 15 existing no

5. Internal pull up on die.

6. Internally tied to GND in the PC745 255

present. This signal is not a power supply input.

MCP

C13

Low

Input

–

–

NC (No

-

Connect)

B7, B8, C3, C6, C8, D5, D6, H4, J16, A4, A5, A2, A3, B5

–

–

–

–

OVDD

C7, E5, E7, E10, E12, G3, G5, G12, G14, K3, K5, K12, K14,

M5, M7, M10, M12, P7, P10

–

–

1.8V/2.0V

3.3V

PLL_CFG[0

A8, B9, A9, D9

High

Input

–

–

QACK

D3

Low

Input

–

–

QREQ

J3

Low

Output

–

–

RSRV

D1

Low

Output

–

–

SMI

A16

Low

Input

–

–

SRESET

B14

Low

Input

–

–

SYSCLK

C9

–

Input

–

–

TA

H14

Low

Input

–

–

TBEN

C2

High

Input

–

–

TBST

A14

Low

I/O

–

–

TCK

C11

High

Input

–

–

TDI(5)

A11

High

Input

–

–

TDO

A12

High

Output

–

–

TEA

H13

Low

Input

–

–

TLBISYNC

C4

Low

Input

–

–

TMS(5)

B11

High

Input

–

–

TRST(5)

C10

Low

Input

–

–

TS

J13

Low

I/O

–

–

TSIZ[0

A13, D10, B12

High

Output

–

–

TT[0

B13, A15, B16, C14, C15

High

I/O

–

–

WT

D2

Low

Output

–

–

V

F6, F8, F9, F11, G7, G10, H6, H8, H9, H11, J6, J8, J9, J11,

K7, K10, L6, L8, L9, L11

–

–

2V

2V

VOLTDET(6)

F3

High

Output

–

–

Table 1. Pinout Listing for the PC745, 255 PBGA Package (Continued)

Signal Name

Pin Number

Active

I/O

1.8V/2.0V

3.3V