PC755CVGU366LE datasheet(34/50 Pages) ATMEL

34 / 50 page

PC755/745

2138D–HIREL–06/03

Figure 22 provides the test access port timing diagram.

Figure 22. Test Access Port Timing Diagram

JTAG Configuration Signals

Boundary scan testing is enabled through the JTAG interface signals. The TRST signal

is optional in the IEEE 1149.1 specification, but is provided on all processors that imple-

ment the PowerPC architecture. While it is possible to force the TAP controller to the

reset state using only the TCK and TMS signals, more reliable power-on reset perfor-

mance will be obtained if the TRST signal is asserted during power-on reset. Because

the JTAG interface is also used for accessing the common on-chip processor (COP)

function, simply tying TRST to HRESET is not practical.

The COP function of these processors allows a remote computer system (typically, a PC

with dedicated hardware and debugging software) to access and control the internal

operations of the processor. The COP interface connects primarily through the JTAG

port of the processor, with some additional status monitoring signals. The COP port

requires the ability to independently assert HRESET or TRST in order to fully control the

processor. If the target system has independent reset sources, such as voltage moni-

tors, watchdog timers, power supply failures, or push-button switches, then the COP

reset signals must bemerged into these signals with logic.

The arrangement shown in Figure 23 allows the COP port to independently assert

HRESET or TRST, while ensuring that the target can drive HRESET as well. If the JTAG

interface and COP header will not be used, TRST should be tied to HRESET through a

Ω isolation resistor so that it is asserted when the systemreset signal (HRESET) is

asserted ensuring that the JTAG scan chain is initialized during power-on. While Motor-

ola recommends that the COP header be designed into the system as shown in Figure

23, if this is not possible, the isolation resistor will allow future access to TRST in the

casewhere a JTAG interfacemay need to be wired onto the system in debug situations.

The COP header shown in Figure 23 adds many benefits — breakpoints, watchpoints,

are possible through this interface — and can be as inexpensive as an unpopulated

footprint for a header to be added when needed.

The COP interface has a standard header for connection to the target system, based on

the 0.025" square-post 0.100" centered header assembly (often called a Berg header).

The connector typically has pin 14 removed as a connector key.

TCK

TDI, TMS

TDO

VM = Midpoint Voltage (OVDD/2)

TDO

t IXJH

t IVJH

tJLOV

tJLOZ

INPUT

DATA VALID

OUTPUT

tJLOH

DATA

VALID

OUTPUT DATA VALID

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