MB9BF412RPMC-G-JNE2 datasheet(3/112 Pages) CYPRESS

3 / 112 page

Document Number: 002-05615 Rev. *D

Page

3 of 112

MB9B410R Series

Quadrature Position/Revolution Counter (QPRC)

(Max three channels)

The Quadrature Position/Revolution Counter (QPRC) is used

to measure the position of the position encoder. Moreover, it

is possible to use up/down counter.

The detection edge of the three external event input pins AIN,

BIN and ZIN is configurable.

16-bit position counter

16-bit revolution counter

Two 16-bit compare registers

Dual Timer (32-/16-bit Down Counter)

The Dual Timer consists of two programmable 32-/16-bit

down counters.

Operation mode is selectable from the followings for each

channel.

Free-running

Periodic (=Reload)

One-shot

Watch Counter

The Watch counter is used for wake up from power

consumption mode.

Interval timer: up to 64 s (Max) @ Sub Clock: 32.768 kHz

External Interrupt Controller Unit

Up to 16 external interrupt input pin

Include one non-maskable interrupt (NMI)

Watchdog Timer (Two channels)

A watchdog timer can generate interrupts or a reset when a

time-out value is reached.

This series consists of two different watchdogs, a "Hardware"

watchdog and a "Software" watchdog.

"Hardware" watchdog timer is clocked by low-speed internal

CR oscillator. Therefore, "Hardware" watchdog is active in

any power consumption mode except Stop mode.

CRC (Cyclic Redundancy Check) Accelerator

The CRC accelerator helps a verify data transmission or

storage integrity.

CCITT CRC16 and IEEE-802.3 CRC32 are supported.

CCITT CRC16 Generator Polynomial: 0x1021

IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7

Clock and Reset

Clocks

Five clock sources (2 external oscillators, 2 internal CR

oscillator, and Main PLL) that are dynamically selectable.



Main Clock:

4 MHz to 48 MHz



Sub Clock:

32.768 kHz



High-speed internal CR Clock:

4 MHz



Low-speed internal CR Clock:

100 kHz

Resets



Reset requests from INITX pin



Power on reset



Software reset



Watchdog timers reset



Low-voltage detector reset



Clock supervisor reset

Clock Super Visor (CSV)

Clocks generated by internal CR oscillators are used to

supervise abnormality of the external clocks.

External OSC clock failure (clock stop) is detected, reset is

asserted.

External OSC frequency anomaly is detected, interrupt or

reset is asserted.

Low-Voltage Detector (LVD)

This Series include 2-stage monitoring of voltage on the VCC

pins. When the voltage falls below the voltage has been set,

Low-Voltage Detector generates an interrupt or reset.

LVD1: error reporting via interrupt

LVD2: auto-reset operation

Low-Power Consumption Mode

Three power consumption modes supported.

Sleep

Timer

Stop

Debug

Serial Wire JTAG Debug Port (SWJ-DP)

Embedded Trace Macrocells (ETM) provide comprehensive

debug and trace facilities.

Power Supply

Wide range voltage:

VCC = 2.7 V to 5.5 V

MB9BF412RPMC-G-JNE2 数据表(PDF) 3 Page - Cypress Semiconductor

MB9BF412RPMC-G-JNE2 数据表(HTML) 3 Page - Cypress Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载