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MB9BF412RPMC-G-JNE2 数据表(PDF) 4 Page - Cypress Semiconductor

部件名 MB9BF412RPMC-G-JNE2
功能描述  32-bit Arm짰 Cortex짰-M3 FM3 Microcontroller
PDF  112 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor

MB9BF412RPMC-G-JNE2 数据表(HTML) 4 Page - Cypress Semiconductor

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Document Number: 002-05615 Rev. *D
Page
4 of 112
MB9B410R Series
Table of Contents
Features
.............................................................................................................................................................................. 1
1.
Product Lineup ............................................................................................................................................................ 6
2.
Packages...................................................................................................................................................................... 8
3.
Pin Assignments ......................................................................................................................................................... 9
4.
List of Pin Functions ................................................................................................................................................. 13
5.
I/O Circuit Type .......................................................................................................................................................... 40
6.
Handling Precautions................................................................................................................................................ 45
6.1
Precautions for Product Design ................................................................................................................................ 45
6.2
Precautions for Package Mounting ........................................................................................................................... 46
6.3
Precautions for Use Environment ............................................................................................................................. 48
7.
Handling Devices....................................................................................................................................................... 49
8.
Block Diagram ........................................................................................................................................................... 51
9.
Memory Size .............................................................................................................................................................. 51
10.
Memory Map .............................................................................................................................................................. 52
11.
Pin Status in Each CPU State ................................................................................................................................... 56
12.
Electrical Characteristics.......................................................................................................................................... 60
12.1
Absolute Maximum Ratings ...................................................................................................................................... 60
12.2
Recommended Operating Conditions....................................................................................................................... 62
12.3
DC Characteristics.................................................................................................................................................... 63
12.3.1
Current Rating ....................................................................................................................................................... 63
12.3.2
Pin Characteristics ................................................................................................................................................. 65
12.4
AC Characteristics .................................................................................................................................................... 67
12.4.1
Main Clock Input Characteristics ........................................................................................................................... 67
12.4.2
Sub Clock Input Characteristics ............................................................................................................................. 68
12.4.3
Internal CR Oscillation Characteristics................................................................................................................... 68
12.4.4
Operating Conditions of Main PLL (In the case of using main clock for input of PLL)............................................ 69
12.4.5
Operating Conditions of Main PLL (In the case of using high-speed internal CR) ................................................. 69
12.4.6
Reset Input Characteristics.................................................................................................................................... 70
12.4.7
Power-on Reset Timing ......................................................................................................................................... 70
12.4.8
External Bus Timing............................................................................................................................................... 71
12.4.9
Base Timer Input Timing........................................................................................................................................ 80
12.4.10
CSIO/UART Timing................................................................................................................................................ 81
12.4.11
External Input Timing ............................................................................................................................................. 89
12.4.12
Quadrature Position/Revolution Counter timing ..................................................................................................... 90
12.4.13
I2C Timing .............................................................................................................................................................. 92
12.4.14
ETM Timing ........................................................................................................................................................... 93
12.4.15
JTAG Timing.......................................................................................................................................................... 94
12.5
12-bit A/D Converter ................................................................................................................................................. 95
12.6
Low-Voltage Detection Characteristics ..................................................................................................................... 98
12.6.1
Low-Voltage Detection Reset ................................................................................................................................ 98
12.6.2
Interrupt of Low-Voltage Detection ........................................................................................................................ 98
12.7
MainFlash Memory Write/Erase Characteristics ....................................................................................................... 99
12.7.1
Write / Erase time .................................................................................................................................................. 99
12.7.2
Erase/write cycles and data hold time.................................................................................................................... 99
12.8
WorkFlash Memory Write/Erase Characteristics ...................................................................................................... 99
12.8.1
Write / Erase time .................................................................................................................................................. 99
12.8.2
Erase/write cycles and data hold time.................................................................................................................... 99



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