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MB9BF412RPMC-G-JNE2 数据表(PDF) 88 Page - Cypress Semiconductor |
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MB9BF412RPMC-G-JNE2 数据表(HTML) 88 Page - Cypress Semiconductor |
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88 / 112 page  Document Number: 002-05615 Rev. *D Page 88 of 112 MB9B410R Series Master mode Slave mode UART external clock input (EXT = 1) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Conditions Min Max Unit Remarks Serial clock L pulse width tSLSH CL = 30 pF tCYCP + 10 - ns Serial clock H pulse width tSHSL tCYCP + 10 - ns SCK fall time tF - 5 ns SCK rise time tR - 5 ns tSCYC tSLOVI VOL VOH VOH VOH VOL VOH VOL VIH VIL VIH VIL tIVSHI tSHIXI tSOVHI SCK SOT SIN tSHSL tR tSLSH tF tSLOVE VIL VIL VIL VIH VIH VOH VOL VOH VOL VIH VIL VIH VIL tIVSHE tSHIXE SCK SOT SIN tSHSL VIL VIL VIL VIH VIH tR tF tSLSH SCK |
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