PRELIMINARY

CY2VC511

Document Number: 001-10796 Rev. *D

Page 3 of 7

VCXO and VIN

The output frequency of the device is adjusted over a limited

range by use of the VCXO feature. This feature is typically used

to phase and frequency lock to a separate reference clock. The

frequency is controlled by the analog voltage on the VIN pin. The

nominal output frequency is generated when VIN = 1.65V. As the

voltage on VIN is increased, the output frequency increases. The

between output frequency (ppm) to VIN voltage is very linear

over a large portion of the control voltage range.

Application Information

Power Supply Filtering Techniques

As in any high speed analog circuitry, noise on the power supply

pins can degrade device performance. For general power plane

decoupling, make certain there is at least one tantalum capacitor

(~5 to 10

μF) in the general vicinity of this device. Additionally,

ensure there is one or two multi-layer ceramic chip capacitors

(0.01 or 0.1

μF) located as close as possible to the power and

ground pins of the device. Ensure the layout is optimized to

minimize power and ground inductance and locate the capacitor

as close to the device pins as possible.

Frequency Table

Input

Output Frequency (MHz)

Reference Frequency (MHz)

PLL Multiplier Value

27

1

27

Absolute Maximum Conditions

Parameter

Description

Condition

Min

Max

Unit

Supply Voltage

–0.5

4.4

V

[1]

Input Voltage, DC

–0.5

V

Temperature, Storage

Non operating

–65

150

°C

Temperature, Junction

–

125

°C

ESD Protection (Human Body Model)

JEDEC STD 22-A114-B

2000

–

V

UL–94

Flammability Rating

At 1/8 in

V–0

Θ

JA

[2]

Thermal Resistance, Junction to

Ambient

0 m/s airflow

84

°C/W

1 m/s airflow

79

2.5 m/s airflow

76

Operating Conditions

Parameter

Description

Min

Typ

Max

Unit

Supply Voltage Range

3.135

3.3

3.465

V

Ambient Temperature

0

–

70

°C

is monotonic)

0.05

–

500

ms

Load Capacitance on CLK output

–

–

15

pF

Notes

1. The voltage on any input or output pin cannot exceed the power pin during power up.

2. Simulated using Apache Sentinel TI software. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of

copper (2/1/1/2 oz.). The internal layers are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model.

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