M69AW048B datasheet(8/29 Pages) STMICROELECTRONICS

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M69AW048B

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OPERATION

Operational modes are determined by device con-

trol inputs W, E1, E2, LB and UB as summarized

the

Operating

Modes

table

(see

Table

2., Operating Modes).

Power-Up Sequence

Because

the

internal

control

logic

the

M69AW048B needs to be initialized, the following

Power-Up procedure must be followed before the

memory is used:

–

Apply power and wait for VCC to stabilize,

–

Wait 300µs while driving both Chip Enable

signals (E1 and E2) High.

See also Figure 24. for details on the Power-Up

AC waveforms.

Read Mode

The device is in Read mode when:

–

Write Enable (W) is High and

–

Output Enable (G) Low and

–

the two Chip Enable signals are asserted

(E1 is Low, and E2 is High).

The time taken to enter Read mode (tELQV, tGLQV

or tBLQV) depends on which of the above signals

was the last to reach the appropriate level.

Data out (DQ15-DQ0) may be indeterminate dur-

ing tELQX, tGLQX and tBLQX but data will always be

valid during tAVQV. See Figures 7, 8, 9, 10 and 11

and Table 11., Read Mode AC Characteristics, for

details of when the outputs become valid.

Write Mode

The device is in Write mode when

–

Write Enable (W) is Low and

–

Chip Enable (E1) is Low and E2 is High

–

at least one of Upper Byte Enable (UB)

and Lower Byte Enable (LB) is Low.

The Write cycle begins just after the event (the fall-

ing edge) that causes the last of these conditions

to become true (tAVWL or tAVEL or tAVBL).

The Write cycle is terminated by the rising edge of

Write Enable (W) or Chip Enable (E1), whichever

occurs first.

If the device is in Write mode (Chip Enable (E1) is

Low, Output Enable (G) is Low, Upper Byte En-

able (UB) and/or Lower Byte Enable (LB) is Low,

then Write Enable (W) will return the outputs to

high impedance within tWHDZ of its rising edge.

Care must be taken to avoid bus contention in this

type of operation. Data input must be valid for tD-

VWH before the rising edge of Write Enable (W), or

for tDVEH before the rising edge of Chip Enable

(E1), whichever occurs first, and remain valid for

tBHDZ, tWHDZ, tEHDZ.

See Figures 12, 13, 14, 15, 16 and 17 and Table

12., Write Mode AC Characteristics, for details of

when the outputs become valid.

Standby Mode

The device is in Standby mode when:

–

Chip Enable (E1)is High and

–

Chip Enable (E2) is High

The input/output buffers and the decoding/control

logic are switched off, but the dynamic array con-

tinues to be refreshed. In this mode, the memory

current consumption, ISB, is reduced, and the data

remains valid.

See Figures 17 and Table 13., Standby/Power-

Down Mode AC Characteristics, for details of

when the outputs become valid.

Power-down Modes

Description of Power-Down Modes. The

M69AW048B has four Power-down modes, Deep

Power-Down, 4 Mbit Partial Array Refresh, 8 Mbit

Partial Array Refresh, and 16 Mbit Partial Array

Refresh (see Table 4. and Figure 22.).

These can be entered using a series of read and

write operations. Each mode has following fea-

tures. The default state is Deep Power-Down and

it is the lowest power consumption but all data will

be lost once E2 is brought Low for Power-down.

No sequence is required to put the device in Deep

Power-Down mode after Power-up.

The device is in one of the Power-down modes

when:

–

Chip Enable (E2) is Low

All the device logic is switched off and all internal

operations are suspended. This gives the lowest

power consumption. In this operating mode, no re-

fresh is performed, and data is lost if the duration

is longer than 10ns. This mode is useful for those

applications where the data contents are no longer

needed, and can be lost, but where reduced cur-

rent consumption is of major importance.

Power-Down Program Sequence. The Power-

Down Program sequence is used to program the

Power-Down Configuration. It requires a total of

six read and write operations, with specific ad-

dresses and data. Between each read or write op-

eration the device must be in Standby mode.

Table 4. shows the sequence. In the first cycle, the

Byte at the highest memory address (MSB) is read.

In the second and third cycles, the data (RDa) read

by first cycle are written back. If the third cycle is

written into a different address, the sequence is

aborted, and the data written by the third cycle is

valid as in a normal write operation. In the fourth

and fifth cycles, the Power-Down Configuration

data is written. The data of the fourth cycle must be

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