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M69AW048B 数据表(PDF) 18 Page - STMicroelectronics |
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M69AW048B 数据表(HTML) 18 Page - STMicroelectronics |
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18 / 29 page ![]() M69AW048B 18/29 Table 12. Write Mode AC Characteristics Note: 1. Maximum value is applicable if E1 is kept Low without any address change. If needed by system operation, please contact your local ST representative for relaxation of the 1000ns limitation. 2. Minimum value must be equal to or greater than the sum of write pulse ( tELEH, tWLBH or tBLBH) and write recovery time (tEHAX, tWHAX or tBHAX). 3. Write pulse is defined from the falling edge of E1, W, or LB/UB, whichever occurs last. 4. Write recovery is defined from Write pulse is defined from the rising edge of E1, W, or LB/UB, whichever occurs first. 5. Applicable to any address change when E1 stays Low. 6. If G is Low after minimum tGHEL, the read cycle is initiated. In other words, G must be brought High within 5ns after E1 is brought Low. Once the read cycle is initiated, new write pulse should be input after minimum Read Cycle Time is met. 7. If G is Low after new address input, the read cycle is initiated. In other words, G must be brought High at the same time or before new address valid. Once the read cycle is initiated, new write pulse should be input after minimum Read Cycle Time is met. Symbol Alt. Parameter M69AW048B Unit Min Max tAVAX (1,2) tWC Write Cycle Time 70 1000 ns tAVBL (2) tAS Address Valid to LB, UB Low 0 ns tAVEL (2) tAS Address Valid to Chip Enable Low 0 ns tAVWL (2) tAS Address Valid to Write Enable Low 0 ns tAXAV (5) tAXW Address Invalid Time for Write 10 ns tBHAX (4) tBR LB, UB High to Address Transition 15 1000 ns tBHDZ tDH LB, UB High to Input High-Z 0 ns tBLBH (3) tBW LB, UB Low to LB, UB High 45 ns tBLBH2 tBWO LB, UB Low to LB, UB High for Page Access 20 ns tBLWH (3) tBW LB, UB Low to Write Enable High 45 ns tDVBH tDS Input Valid to LB, UB High 20 ns tDVEH tDS Input Valid to Chip Enable High 20 ns tDVWH tDS Input Valid to Write Enable High 20 ns tEHAX (4) tWRC Chip Enable High to Address Transition 15 ns tEHDZ tDH Chip Enable High to Input High-Z 0 ns tEHEL tCP Chip Enable High to Chip Enable Low 15 ns tELAX (1,2) tWC Write Cycle Time 70 1000 ns tELEH (3) tCW Chip Enable Low to Chip Enable High 45 ns tGHAV (7) tOES Output Enable High to Address Valid 0 ns tGHEL (6) tOHCL Output Enable High to Chip Enable Low –5 ns tGHDZ (4) tOHZ Output Enable High to Output Hi-Z 20 ns tWHAX (4) tWR Write Enable High to Address Transition 15 1000 ns tWHDZ tDH Write Enable High to Input High-Z 0 ns tWLBH (3) tWP Write Enable Low to LB, UB High 45 ns tWLWH (3) tWP Write Enable Low to Write Enable High 45 ns |
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